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187 条记录 (耗时 0.016 秒)

    Test period generator for automatic test equipment
    61.
    发明公开
    Test period generator for automatic test equipment 失效
    Prüfperiodengeneratorfürautomatische Testanordnung。

    公开(公告)号：EP0136207A1

    公开(公告)日：1985-04-03

    申请号：EP84401610.5

    申请日：1984-08-01

    申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

    发明人： West, Burnell G. ,  Herlein, Richard F.

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31935 ,  G01R31/31713 ,  G01R31/3191 ,  G01R31/31922 ,  G01R31/31924 ,  G01R31/31926 ,  G01R31/31928 ,  G01R31/31937 ,  G11C7/22 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00247 ,  H03K2005/00254 ,  H03K2005/0026

    摘要： A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators. Each of the three period generators includes two interconnected timing interval generators 30 and 40 that alternately generate overlapping timing signals. Each timing interval generator includes a stop-restart oscillator 32, a counter 34, and a delay-line vernier 36. Upon the receipt of a start signal, the oscillator stops and restarts to align its clock pulses to the start signal. The oscillator output clocks the counter, which supplies a signal to the vernier when a preselected number is reached. The vernier delays the counter signal by a preselected delay and issus a signal that designates the end of the period.

    摘要翻译： 定时子系统10包括若干测试周期发生器，用于向被测设备提供各种定时信号。 主，次要和自由运行周期发生器各自向多路复用器18提供各种定时信号，多路复用器18选择性地将定时信号连接到定时发生器20.中央处理单元28向周期发生器和定时发生器提供数据以定义它们各自的定时 信号。 由主周期发生器12产生的定时信号定义总体测试速率。 次周期发生器14在主时钟信号的周期内产生多个定时信号以允许更高的时钟速率。 与主时钟周期无关的定时信号由自由运行周期发生器16产生。外部同步器电路26提供从被测器件22到主周期发生器的反馈回路。 参考驱动器触发延迟电路27提供用于校准定时发生器的装置。 三个周期发生器中的每一个包括交替地产生重叠定时信号的两个相互连接的定时间隔发生器30和40。 每个定时间隔发生器包括停止重启振荡器32，计数器34和延迟线游标36​​。在接收到起始信号时，振荡器停止并重新启动以将其时钟脉冲对准起始信号。 振荡器输出时钟计数器，当达到预先选定的数字时，该计数器向游标器提供信号。 游标器延迟计数器信号预先设定的延迟并发出指示周期结束的信号。

    Method and apparatus for monitoring automated testing of electronic circuits
    62.
    发明公开
    Method and apparatus for monitoring automated testing of electronic circuits 失效
    为应用和监督的方法和设备的电子电路的自动测试过程中编程的测试信号。

    公开(公告)号：EP0136206A1

    公开(公告)日：1985-04-03

    申请号：EP84401609.7

    申请日：1984-08-01

    申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

    发明人： Schinabeck, John

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31935 ,  G01R31/31713 ,  G01R31/3191 ,  G01R31/31922 ,  G01R31/31924 ,  G01R31/31926 ,  G01R31/31928 ,  G01R31/31937 ,  G11C7/22 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00247 ,  H03K2005/00254 ,  H03K2005/0026

    摘要： A plurality of signal applying and monitoring circuits are coupled to pins of an electronic device being testes to force test stimuli signals representing logic states or other parameters onto input pins of the device under test. The responses to the stimuli signals are monitored while the device is being tested. Each signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a device power supply connected to the node for supplying a test bias signal, a comparison circuit connected to the node for indicating the relative magnitude of the test bias signal with respect to the bias level at the node, and a latch circuit responsive to the output signal produced by the comparison circuit. The device power supply is included for providing test bias signals to test power drain during functional testing. The transitions of the device power supply are monitored and latched for providing a record of the power drain of the device being tested. Other features are also disclosed.

    摘要翻译： 信号施加和监控电路的多个耦合到出名迫使测试激励信号表示走上被测器件的输入引脚的逻辑状态或其他参数的电子设备的引脚。 当设备被测试的刺激信号的响应进行监视。 施加和监测电路中的每个信号包括节点被耦合到所述被测装置的销，连接至节点，用于提供测试偏置信号，连接到节点的比较电路，用于指示的相对大小的设备供电 测试偏置信号相对于节点处的偏置电平，并且响应于通过该比较电路产生的输出信号的锁存电路。 装置电源被包括用于提供测试偏置信号的功能测试期间测试功耗。 电源装置的转换进行监测和锁存用于提供所述设备的功率消耗的一个记录被测试。 其他功能使游离缺失盘。

    Control of signal timing apparatus in automatic test systems using minimal memory
    63.
    发明公开
    Control of signal timing apparatus in automatic test systems using minimal memory 失效
    Kontrolle eines Signaltaktgebers in automatischen Testsystemen unter Verwendung eines Minimalspeichers。

    公开(公告)号：EP0136204A2

    公开(公告)日：1985-04-03

    申请号：EP84401606.3

    申请日：1984-08-01

    申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

    发明人： Herlein, Richard F.

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31935 ,  G01R31/31713 ,  G01R31/3191 ,  G01R31/31922 ,  G01R31/31924 ,  G01R31/31926 ,  G01R31/31928 ,  G01R31/31937 ,  G11C7/22 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00247 ,  H03K2005/00254 ,  H03K2005/0026

    摘要： A system is disclosed which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information related to a base time delay, while a vernier memory stores information relating to timing corrections to be made to the base time delay. The base delay memory controls a counter while the correction memory controls a vernier deskew apparatus for further delaying the output signal from the counter. To prevent carries from the vernier memory from influencing the base delay memory, the most significant bit of the vernier memory is of the same significance as the least significant bit of the base delay memory. The most significant bit of the vernier memory is also connected to drive the counter, in effect providing the counter with two least significant bits, and enabling a single base delay memory to control more than one signal timing paths.

    摘要翻译： 公开了一种能够在自动测试系统中以精确期望的时间提供信号的系统。 该装置包括存储与基本时间延迟有关的信息的基本延迟存储器，而游标存储器存储与基本时间延迟相关的定时校正的信息。 基本延迟存储器控制计数器，而校正存储器控制游标去偏移装置，用于进一步延迟来自计数器的输出信号。 为了防止游标存储器的进位影响基本延迟存储器，游标存储器的最高有效位与基本延迟存储器的最低有效位具有相同的意义。 游标存储器的最高有效位也被连接以驱动计数器，实际上为计数器提供两个最低有效位，并且使得单个基本延迟存储器能够控制多于一个信号定时路径。

    Apparatus for testing thyristor valve
    64.
    发明公开
    Apparatus for testing thyristor valve 审中-公开
    Verfahren zumPrüfeneines Thyristors

    公开(公告)号：EP2667210A2

    公开(公告)日：2013-11-27

    申请号：EP13167596.9

    申请日：2013-05-14

    申请人： LSIS Co., Ltd. ,  Myongji University Industry and Academia Cooperation Foundation

    发明人： Baek, Seung Taek ,  Han, Byung Moon ,  Nho, Eui Cheol ,  Chung, Yong Ho ,  Lee, Wook Hwa

    IPC分类号： G01R31/333

    CPC分类号： G01R31/263 ,  G01R31/00 ,  G01R31/31924 ,  G01R31/3336 ,  G01R31/40

    摘要： An apparatus for testing a thyristor valve includes: a current source circuit that provides an electric current when a thyristor valve as a test target is turned on; a voltage source circuit that provides a reverse voltage or a forward voltage when the thyristor valve is turned off; and a first auxiliary valve provided between a connection point between the thyristor valve and the voltage source circuit and the current source circuit, and that insulates the current source circuit from the voltage source circuit to protect the current source circuit from a high voltage of the voltage source circuit.

    摘要翻译： 一种用于测试晶闸管阀的装置，包括：电流源电路，当作为测试对象的晶闸管阀门导通时，提供电流; 在晶闸管阀关闭时提供反向电压或正向电压的电压源电路; 以及第一辅助阀，设置在晶闸管阀和电压源电路之间的连接点与电流源电路之间，并且使电流源电路与电压源电路绝缘，以保护电流源电路免受电压的高电压 源电路。

    METHOD FOR TESTING A PARTIALLY ASSEMBLED MULTI-DIE DEVICE, INTEGRATED CIRCUIT DIE AND MULTI-DIE DEVICE
    66.
    发明授权
    METHOD FOR TESTING A PARTIALLY ASSEMBLED MULTI-DIE DEVICE, INTEGRATED CIRCUIT DIE AND MULTI-DIE DEVICE 有权
    测试方法部分组装更多的芯片装置，集成电路芯片和更多的芯片装置

    公开(公告)号：EP2331979B1

    公开(公告)日：2012-07-04

    申请号：EP09787305.3

    申请日：2009-09-26

    申请人： NXP B.V.

    发明人： JONG, Fransciscus Gerardus Maria De ,  BIEWENGA, Alexander, Sebastian

    IPC分类号： G01R31/3185

    CPC分类号： G01R31/318555 ,  G01R19/00 ,  G01R31/26 ,  G01R31/28 ,  G01R31/31717 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/318558 ,  G01R31/31924

    摘要： The present invention discloses a method of testing a partially assembled multi-die device (1) by providing a carrier (300) comprising a device-level test data input (12) and a device-level test data output (18); placing a first die on the carrier, the first die having a test access port (100c) comprising a primary test data input (142), a secondary test data input (144) and a test data output (152), the test access port being controlled by a test access port controller (110); communicatively coupling the secondary test data input (144) of the first die to the device-level test data input (12), and the test data output (152) of the first die to the device-level test data output (18); providing the first die with configuration information to bring the first die in a state in which the first die accepts test instructions from its secondary test data input (144); testing the first die, said testing including providing the secondary test data input (144) of the first die with test instructions through the device-level test data input (12); and collecting a test result for the first die on the device-level test data output (18). Consequently, a die of a partially assembled multi-die device such as a System-in-Package may be tested using its integrated boundary scan test architecture.

    Supply current based testing of CMOS output stages
    69.
    发明公开
    Supply current based testing of CMOS output stages 有权
    VersorgungsstrombasiertePrüfungvon CMOS-Ausgangsstufen

    公开(公告)号：EP2093580A1

    公开(公告)日：2009-08-26

    申请号：EP08368004.1

    申请日：2008-02-25

    申请人： Dialog Semiconductor GmbH

    发明人： von Staudt, Hans Martin ,  Somerville, Alan

    IPC分类号： G01R31/319 ,  G01R31/30

    CPC分类号： G01R31/31924 ,  G01R31/3008

    摘要： A CMOS driver test configuration, which allows both leakage current and load current testing, using a single monitor, or current meter, located in a power lead of a tester connected to a power pad servicing the driver circuits. Both leakage testing and load current testing for CMOS drivers is described. The test configuration allows a plurality of driver circuits connected in parallel between power pads to be tested simultaneously. An ESD device, internal to the chip, is used as a load during load current testing in chip testing, and an external load is used during package testing in order to include the bonding means between the chip output pad of the driver and the package I/O pin in the current path during load current testing.

    摘要翻译： CMOS驱动器测试配置，允许泄漏电流和负载电流测试，使用单个监视器或电流表，位于连接到维修驱动器电路的电源焊盘的测试仪的电源线中。 描述CMOS驱动器的泄漏测试和负载电流测试。 测试配置允许在电源焊盘之间并联连接的多个驱动电路被同时测试。 在芯片测试中的负载电流测试期间，芯片内部的ESD器件用作负载，并且在封装测试期间使用外部负载，以便在驱动器的芯片输出焊盘和封装I之间包括接合装置 / O引脚在负载电流测试中的当前通路。

    MULTI-STAGE DATA PROCESSOR WITH SIGNAL REPEATER
    70.
    发明授权
    MULTI-STAGE DATA PROCESSOR WITH SIGNAL REPEATER 有权
    与信号中继多级数据处理器

    公开(公告)号：EP1982204B1

    公开(公告)日：2009-04-15

    申请号：EP06708074.7

    申请日：2006-02-07

    申请人： Verigy (Singapore) Pte. Ltd.

    发明人： SERRER, Juergen

    IPC分类号： G01R31/3183

    CPC分类号： G01R31/31924 ,  G01R31/31922

    摘要： A signal processing device (102) comprising a plurality of processing stages (106 to 108), each of the plurality of processing stages (106 to 108) being adapted for applying an input signal to each of at least one item under examination (109) to be coupled to a respective one of the plurality of processing stages (106 to 108), and at least one signal reconditioning unit (116), each of the at least one signal reconditioning unit (116) being adapted for reconditioning the input signal in a signal path between a preceding one of the plurality of processing stages (106) and a subsequent one of the plurality of processing stages (107).