公开(公告)号：EP3198425A1

公开(公告)日：2017-08-02

申请号：EP15781207.4

申请日：2015-09-25

申请人： Microsoft Technology Licensing, LLC

发明人： RADIGAN, James J.

IPC分类号： G06F9/45 ,  G06F9/44 ,  G06F21/12

CPC分类号： G06F8/4435 ,  G06F8/443 ,  G06F8/4442 ,  G06F9/4486 ,  G06F21/52

摘要： A compiler-created cache contains target addresses of multiple indirect routine call sites. Ordinals assigned to indirect routine call sites are used to hardcoded offsets into the cache. Ordinals may be computed using a routine counter and an indirect call site counter. At runtime a target address of an indirect routine call site is compared to an entry in the cache using the hardcoded offset for efficiency. If the target address matches the cache entry, then a redundant call is avoided; otherwise, the call is not redundant, and the cache is updated. The call tested for redundancy may be a security check for malware, or a computationally expensive routine which calculates a return value without any side effects. Stack pointer validity may be checked. The cache may be guarded with code for trustworthy computing. Tail merging may be performed.

摘要翻译： 编译器创建的缓存包含多个间接例程调用站点的目标地址。 分配给间接例程呼叫站点的常规用于将偏移量硬编码到缓存中。 可以使用常规计数器和间接呼叫站点计数器来计算常规。 在运行时，间接例程调用站点的目标地址与高速缓存中的条目进行比较，使用硬编码的偏移量来提高效率。 如果目标地址匹配缓存条目，则避免冗余呼叫; 否则，调用不是多余的，并且更新缓存。 测试冗余的呼叫可能是恶意软件的安全检查，也可能是计算昂贵的例程，计算返回值时没有任何副作用。 可以检查堆栈指针有效性。 缓存可以用可靠计算的代码来保护。 可以执行尾部合并。

公开(公告)号：EP3129887A4

公开(公告)日：2017-07-26

申请号：EP14891605

申请日：2014-12-14

申请人： VIA ALLIANCE SEMICONDUCTOR CO LTD

发明人： HOOKER RODNEY E ,  EDDY COLIN ,  REED DOUGLAS R ,  GREER JOHN MICHAEL

IPC分类号： G06F12/08 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F9/45 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/127

CPC分类号： G06F12/0862 ,  G06F8/4442 ,  G06F9/3455 ,  G06F9/3802 ,  G06F9/383 ,  G06F12/0811 ,  G06F12/0848 ,  G06F12/127 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/502 ,  G06F2212/6026

摘要： A processor includes a first prefetcher that prefetches data in response to memory accesses and a second prefetcher that prefetches data in response to memory accesses. Each of the memory accesses has an associated memory access type (MAT) of a plurality of predetermined MATs. The processor also includes a table that holds first scores that indicate effectiveness of the first prefetcher to prefetch data with respect to the plurality of predetermined MATs and second scores that indicate effectiveness of the second prefetcher to prefetch data with respect to the plurality of predetermined MATs. The first and second prefetchers selectively defer to one another with respect to data prefetches based on their relative scores in the table and the associated MATs of the memory accesses.

摘要翻译： 处理器包括响应于存储器访问而预取数据的第一预取器以及响应于存储器访问而预取数据的第二预取器。 每个存储器访问具有多个预定MAT的相关存储器访问类型（MAT）。 处理器还包括保存指示第一预取器相对于多个预定MAT预取数据的有效性的第一分数以及指示第二预取器相对于多个预定MAT预取数据的有效性的第二分数的表。 第一和第二预取器基于它们在表中的相对分数和存储器访问的相关MAT，选择性地相对于数据预取彼此推迟。

公开(公告)号：EP3049915A4

公开(公告)日：2017-03-08

申请号：EP14891604

申请日：2014-12-14

申请人： VIA ALLIANCE SEMICONDUCTOR CO LTD

发明人： HOOKER RODNEY E ,  EDDY COLIN ,  REED DOUGLAS R ,  GREER JOHN MICHAEL

IPC分类号： G06F9/38

CPC分类号： G06F12/0862 ,  G06F8/4442 ,  G06F9/30043 ,  G06F9/3455 ,  G06F9/3802 ,  G06F9/383 ,  G06F11/30 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/127 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/502 ,  G06F2212/602 ,  G06F2212/6026 ,  Y02D10/13

摘要： A processor includes a prefetcher that prefetches data in response to memory accesses, wherein each memory access has an associated memory access type (MAT) of a plurality of predetermined MATs. The processor also includes a table that holds scores that indicate effectiveness of the prefetcher to prefetch data with respect to the plurality of predetermined MATs. The prefetcher prefetches data in response to memory accesses at a level of aggressiveness based on the scores held in the table and the associated MATs of the memory accesses.

公开(公告)号：EP2885705A1

公开(公告)日：2015-06-24

申请号：EP13731601.4

申请日：2013-06-13

申请人： Qualcomm Incorporated

发明人： RESHADI, Mohammad H. ,  WEBER, Michael

IPC分类号： G06F9/45 ,  G06F17/30

CPC分类号： G06F17/2247 ,  G06F8/4442 ,  G06F17/30902

摘要： The aspects include browser systems and methods of loading/rendering a webpage by preprocessing scripts within the web document (HTML page) in a sandboxed script engine to discover resources not explicitly requested in the web document so such resources can be pre-fetched and downloaded speculatively. The sandboxed execution of scripts and downloading of discovered resources may proceed in parallel with the performance of other browser operations (e.g., HTML parsing) and other resource requests. The sandboxed script engine may be isolated or separated from the other browser components. The sandboxed script engine may operate to speedup the process of identifying resources inconsistent with standard script execution processes.

摘要翻译： 这些方面包括浏览器系统和通过在沙盒脚本引擎中预处理网页文档（HTML页面）内的脚本来加载/呈现网页的方法来发现网络文档中未明确请求的资源，以便可以推测这些资源被预先提取和下载 。 脚本的沙盒执行和发现的资源的下载可以与其他浏览器操作（例如，HTML解析）和其他资源请求的执行并行进行。 沙盒脚本引擎可能与其他浏览器组件隔离或分离。 沙盒脚本引擎可能会加速识别与标准脚本执行过程不一致的资源的过程。

公开(公告)号：EP2562991A4

公开(公告)日：2013-08-14

申请号：EP11783092

申请日：2011-06-03

申请人： HUAWEI TECH CO LTD

发明人： BAO DONG ,  YANG DEPING

IPC分类号： H04L29/08 ,  G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0215 ,  G06F8/4442 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/314 ,  H04L67/2847

公开(公告)号：EP1700209A2

公开(公告)日：2006-09-13

申请号：EP04815332.4

申请日：2004-12-21

申请人： INTEL CORPORATION

发明人： SHPEISMAN, Tatiana ,  ADL-TABATABAI, Ali-Reza

IPC分类号： G06F9/45

CPC分类号： G06F8/441 ,  G06F8/4442

摘要： In one embodiment, a method is provided. The method of this embodiment provides scheduling a sequence of machine-executable instructions, and creating a data layout based on the scheduled sequence of machine-executable instructions.

公开(公告)号：EP1668502A2

公开(公告)日：2006-06-14

申请号：EP04789475.3

申请日：2004-09-30

申请人： INTEL CORPORATION

发明人： LIAO, Shih-wei ,  TIAN, Xinmin ,  HOFLEHNER, Gerolf, F. ,  WANG, Hong ,  LAVERY, Daniel, M. ,  WANG, Perry ,  KIM, Dongkeun ,  GIRKAR, Milind ,  SHEN, John, P.

IPC分类号： G06F9/45

CPC分类号： G06F9/3842 ,  G06F8/4442 ,  G06F9/383 ,  G06F9/3851

摘要： Methods and apparatuses for compiler- created helper thread for multi­threading are described herein. In one embodiment, exemplary process includes identifying a region of a main thread that likely has one or more delinquent loads, the one or more delinquent loads representing loads which likely suffer cache misses during an execution of the main thread, analyzing the region for one or more helper threads with respect to the main thread, and generating code for the one or more helper threads, the one or more helper threads being speculatively executed in parallel with the main thread to perform one or more tasks for the region of the main thread. Other methods and apparatuses are also described.

公开(公告)号：EP1660999A2

公开(公告)日：2006-05-31

申请号：EP04783500.4

申请日：2004-08-26

申请人： MIPS Technologies, Inc.

发明人： KISSELL, Kevin

IPC分类号： G06F9/46 ,  G06F9/30

CPC分类号： G06F9/4881 ,  G06F8/4442 ,  G06F9/3009 ,  G06F9/3851

摘要： A mechanism for processing in a processor enabled to support and execute multiple program threads includes a parameter (602) for scheduling a program thread and an instruction (600) disposed within the program thread and enabled to access the parameter. When the parameter equals a first value the instruction, when issued by a program thread, reschedules the program thread in accordance with one or more conditions encoded within the parameter.

公开(公告)号：EP1570348A2

公开(公告)日：2005-09-07

申请号：EP03775007.2

申请日：2003-11-18

申请人： Interuniversitair Microelektronica Centrum

发明人： MARCHAL, Paul ,  GOMEZ, José, Ignacio ,  BRUNI, Davide ,  CATTHOOR, Francky

IPC分类号： G06F9/45

CPC分类号： G06F8/4432 ,  G06F8/4442 ,  Y02D10/41

摘要： Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system as well as methods, apparatus and software products for run-time memory management techniques of such a system. Memory assignment techniques are described for assigning data to a hierarchical memory particularly for multi-tasked applications where data of dynamically created/deleted tasks is allocated at run-time. The energy consumption of hierarchical memories such as multi-banked memories depends largely on how data is assigned to the memory banks. Methods, apparatus and software products are described for design-time data-assignment techniques for hierarchical memories, e.g., multi-banked memories in an essentially digital system which improve a cost function such as energy consumption.

公开(公告)号：EP1556792A2

公开(公告)日：2005-07-27

申请号：EP03776267.1

申请日：2003-10-10

申请人： Hewlett-Packard Development Company, L.P.

发明人： SCHREIBER, Robert, S. ,  DARTE, Alain

IPC分类号： G06F17/30

CPC分类号： G06F8/4442

摘要： A method of storing data includes the steps of storing data comprising the steps of identifying respective lifetimes of each member of an indexed collection of data element, each of the data elements referenceable in a data index space representing a set of valid data element indices; identifying a set of pairs of the data elements having overlapping lifetimes; and generating a mapping from the data index space to an address offset space based on the set of pairs of the data elements having the overlapping lifetimes.