公开(公告)号：EP3320427A1

公开(公告)日：2018-05-16

申请号：EP16838284.4

申请日：2016-04-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： VINCENT, John Edward ,  SINN, Peter Man Kin ,  WATSON, Benton

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30058 ,  G06F9/30127 ,  G06F9/321 ,  G06F9/322 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/3871

Abstract: Different processor architectures are described to evaluate and track dependencies required by instructions. The processors may hold or queue instructions that require output of other instructions until required data and resources are available which may remove the requirement of NOPs in the instruction memory to resolve dependencies and pipeline hazards. The processor may divide instruction data into bundles for parallel execution and provide speculative execution. The processor may include various components to implement an evaluation unit, execution unit and termination unit.

公开(公告)号：EP3296872A1

公开(公告)日：2018-03-21

申请号：EP16200576.3

申请日：2016-11-24

Applicant: Advanced Micro Devices, Inc.

Inventor： SMAUS, Gregory ,  KING, John ,  ACHENBACH, Michael ,  LEPAK, Kevin ,  RAFACZ, Matthew ,  BAMFORD, Noah

IPC: G06F9/52 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F12/1466 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/528 ,  G06F2212/1052

Abstract: Techniques for improving execution of a lock instruction are provided herein. A lock instruction and younger instructions are allowed to speculatively retire prior to the store portion of the lock instruction committing its value to memory. These instructions thus do not have to wait for the lock instruction to complete before retiring. In the event that the processor detects a violation of the atomic or fencing properties of the lock instruction prior to committing the value of the lock instruction, the processor rolls back state and executes the lock instruction in a slow mode in which younger instructions are not allowed to retire until the stored value of the lock instruction is committed. Speculative retirement of these instructions results in increased processing speed, as instructions no longer need to wait to retire after execution of a lock instruction.

Abstract translation: 这里提供了用于改进锁定指令的执行的技术。 允许锁定指令和更年轻的指令在锁定指令的存储部分提交给存储器之前推测性地退出。 这些指令因此不必在退休之前等待锁定指令完成。 如果处理器在提交锁定指令的值之前检测到违反了锁定指令的原子或防护属性，则处理器回滚状态并以缓慢模式执行锁定指令，其中不允许年轻的指令 退出直到锁定指令的存储值被提交。 这些指令的推测退役导致处理速度增加，因为指令不再需要在执行锁定指令后等待退休。

公开(公告)号：EP2776919B1

公开(公告)日：2017-09-06

申请号：EP12784387.8

申请日：2012-10-11

Applicant: Oracle International Corporation

Inventor： CHOU, Yuan, C. ,  MAHURIN, Eric, W.

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3842 ,  G06F9/30127 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3865

公开(公告)号：EP3198403A1

公开(公告)日：2017-08-02

申请号：EP15845271.4

申请日：2015-08-31

Applicant: Intel Corporation

Inventor： WANG, Cheng ,  WU, Youfeng ,  SANKARAN, Rajesh M.

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30145 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/466 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0875 ,  G06F2212/452

Abstract: A processor of an aspect includes a decode unit to decode a persistent store fence instruction. The processor also includes a memory subsystem module coupled with the decode unit. The memory subsystem module, in response to the persistent store fence instruction, is to ensure that a given data corresponding to the persistent store fence instruction is stored persistently in a persistent storage before data of all subsequent store instructions is stored persistently in the persistent storage. The subsequent store instructions occur after the persistent store fence instruction in original program order. Other processors, methods, systems, and articles of manufacture are also disclosed.

Abstract translation: 一个方面的处理器包括解码单元以解码持久存储围栏指令。 处理器还包括与解码单元耦合的存储器子系统模块。 响应于持久性存储围栏指令，存储器子系统模块将确保与持久存储围栏指令相对应的给定数据在所有后续存储指令的数据永久存储在持久性存储中之前永久存储在持久性存储中。 随后的存储指令在原始程序顺序中的持久存储围栏指令之后发生。 还公开了其他处理器，方法，系统和制造物品。

公开(公告)号：EP2791785A4

公开(公告)日：2017-01-18

申请号：EP11877535

申请日：2011-12-16

Applicant: INTEL CORP

Inventor： KRISHNASWAMY ARVIND ,  LAVERY DANIEL M

IPC: G06F9/45 ,  G06F9/30 ,  G06F9/305 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46

CPC classification number: G06F9/3861 ,  G06F8/49 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30174 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/45525 ,  G06F9/467

Abstract: A method and system uses exceptions for code specialization in a system that supports transactions. The method and system includes inserting one or more branchless instructions into a sequence of computer instructions. The branchless instructions include one or more instructions that are executable if a commonly occurring condition is satisfied and include one or more instructions that are configured to raise an exception if the commonly occurring condition is not satisfied.

Abstract translation: 方法和系统在支持事务的系统中使用异常代码专门化。 该方法和系统包括将一个或多个无分支指令插入到一系列计算机指令中。 无分支指令包括一个或多个可执行的指令，如果共同发生的条件被满足并且包括如果共同发生的条件不被满足则配置成引发异常的一个或多个指令。

公开(公告)号：EP2695078B1

公开(公告)日：2016-10-19

申请号：EP12768614.5

申请日：2012-04-06

Applicant: VIA Technologies, Inc.

Inventor： HENRY, G. Glenn ,  COL, Gerard M. ,  EDDY, Colin ,  HOOKER, Rodney E. ,  PARKS, Terry

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3859

公开(公告)号：EP2671150B1

公开(公告)日：2014-12-31

申请号：EP12704208.3

申请日：2012-02-06

Applicant: Qualcomm Incorporated

Inventor： DOCKSER, Kenneth Alan ,  TEKMEN, Yusuf Cagatay

IPC: G06F9/38

CPC classification number: G06F9/3814 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3859 ,  G06F9/3877 ,  G06F9/3885

公开(公告)号：EP2671150A1

公开(公告)日：2013-12-11

申请号：EP12704208.3

申请日：2012-02-06

Applicant: Qualcomm Incorporated

Inventor： DOCKSER, Kenneth Alan ,  TEKMEN, Yusuf Cagatay

IPC: G06F9/38

CPC classification number: G06F9/3814 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3859 ,  G06F9/3877 ,  G06F9/3885

Abstract: Apparatus and methods provide early access of instructions. A fetch queue is coupled to an instruction cache and configured to store a mix of processor instructions for a first processor and coprocessor instructions for a second processor. A coprocessor instruction selector is coupled to the fetch queue and configured to copy coprocessor instructions from the fetch queue. A queue is coupled to the coprocessor instruction selector and from which coprocessor instructions are accessed for execution before the coprocessor instruction is issued to the first processor. Execution of the copied coprocessor instruction is started in the coprocessor before the coprocessor instruction is issued to a processor. The execution of the copied coprocessor instruction is completed based on information received from the processor after the coprocessor instruction has been issued to the processor.

公开(公告)号：EP2104032B1

公开(公告)日：2012-01-11

申请号：EP08168555.4

申请日：2008-11-07

Applicant: Fujitsu Limited

Inventor： Yoshida, Toshio c/o Fujitsu Limited

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3887

公开(公告)号：EP2332043A1

公开(公告)日：2011-06-15

申请号：EP09789014.9

申请日：2009-07-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： CHRISTIE, David, S. ,  HOHMUTH, Michael, P. ,  DIESTELHORST, Stephan

IPC: G06F9/455 ,  G06F9/46

CPC classification number: G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/468 ,  G06F9/52

Abstract: A system and method are disclosed wherein a processor of a plurality of processors coupled to shared memory, is configured to initiate execution of a section of code according to a first transactional mode of the processor. The processor is configured to execute a plurality of protected memory access operations to the shared memory within the section of code as a single atomic transaction with respect to the plurality of processors. The processor is further configured to initiate, within the section of code, execution of a subsection of the section of code according to a second transactional mode of the processor, wherein the first and second transactional modes are each associated with respective recovery actions that the processor is configured to perform in response to detecting an abort condition.

Abstract translation: 公开了一种系统和方法，其中耦合到共享存储器的多个处理器的处理器被配置为根据处理器的第一事务模式启动执行代码段。 所述处理器被配置为对所述代码段内的所述共享存储器执行对所述多个处理器的单个原子事务的多个受保护存储器访问操作。 处理器还被配置为在代码段内启动根据处理器的第二事务模式执行代码段的子部分，其中第一和第二事务模式各自与相应的恢复动作相关联，处理器 被配置为响应于检测到中止条件而执行。