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197 条记录 (耗时 0.013 秒)

    Compact analog-multiplexed global sense amplifier for rams
    61.
    发明公开
    Compact analog-multiplexed global sense amplifier for rams 审中-公开
    Kompacter操作复全球Leseversterker的RAM

    公开(公告)号：EP1278197A3

    公开(公告)日：2006-04-12

    申请号：EP02090245.8

    申请日：2002-07-11

    申请人： Broadcom Corporation

    发明人： Issa, Sami

    IPC分类号： G11C7/18 ,  G11C5/02 ,  G11C7/10

    CPC分类号： G11C11/4097 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002 ,  G11C2207/104

    摘要： The method and system of the present invention superimposes read and write operations by connecting the global bit lines that are not selected to the Vdd. The respective local sense amplifiers for the non-selected global bit lines just read and refresh the respective memory cells resulting in smaller local sense amplifiers and one global sense amplifiers for several memory cells (and local sense amplifiers).
    In one embodiment, eight global bit lines are shared by one global sense amplifier and are multiplexed. Only one global bit line pair generates voltage development as an input to a respective local sense amplifier during a write operation, while the other three global bit line pairs are disconnected from their respective local sense amplifiers and thus have no voltage development. Thus, the respective activated sense amplifiers amplify only the cell data which reassembles a read and refresh operation.

    Common bit/common source line high density 1T1R resistive-ram array
    65.
    发明公开
    Common bit/common source line high density 1T1R resistive-ram array 有权
    Hochdichte 1T1R电阻式RAM-Speichermatrix mit einer gemeinsamen Bitleitung und einer gemeinsamen Sourceleitung

    公开(公告)号：EP1424697A2

    公开(公告)日：2004-06-02

    申请号：EP03254605.3

    申请日：2003-07-24

    申请人： SHARP KABUSHIKI KAISHA

    发明人： Hsu, Sheng Teng

    IPC分类号： G11C7/18 ,  G11C11/16

    CPC分类号： G11C13/0007 ,  G11C7/18 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/79

    摘要： A common bit/common source line high density 1T1R (one transistor/one resistor) R-RAM array, and method for operating said array are provided. The R-RAM array comprises a first transistor with a drain connected to a non-shared bit line with a first memory resistor. The gates of the first, second, third, and fourth transistors are sequentially connected to a common word line. The R-RAM array comprises at least one common bit line. A second memory resistor is interposed between the drain of the second transistor and the common bit line. Likewise, a third memory resistor is interposed between the drain of the third transistor and the common bit line. A common source line is connected to the sources of the third and fourth transistors. The R-RAM array comprises m rows of n sequential transistors.

    摘要翻译： 提供公共位/公共源线高密度1T1R（一个晶体管/一个电阻器）R-RAM阵列，以及用于操作所述阵列的方法。 R-RAM阵列包括具有与第一存储电阻器连接到非共享位线的漏极的第一晶体管。 第一，第二，第三和第四晶体管的栅极依次连接到公共字线。 R-RAM阵列包括至少一个公共位线。 第二存储电阻器插在第二晶体管的漏极和公共位线之间。 同样，在第三晶体管的漏极和公共位线之间插入第三存储电阻。 公共源极线连接到第三和第四晶体管的源极。 R-RAM阵列包括m行n个顺序晶体管。

    Pseudo differential sensing method and apparatus for dram cell
    67.
    发明公开
    Pseudo differential sensing method and apparatus for dram cell 有权
    Verfahren und Anordnung zum pseudodifferentiellen Datenlesen aus einer DRAM Zelle

    公开(公告)号：EP1241676A1

    公开(公告)日：2002-09-18

    申请号：EP02090079.1

    申请日：2002-02-28

    申请人： Broadcom Corporation

    发明人： Issa, Sami ,  Afghahi, Morteza Cyrus

    IPC分类号： G11C11/4094 ,  G11C11/4097 ,  G11C11/4099 ,  G11C11/4091 ,  G11C11/405 ,  G11C7/12 ,  G11C7/18 ,  G11C7/14 ,  G11C7/06

    CPC分类号： G11C11/4097 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/18 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099

    摘要： Present invention describes an efficient implementation of differential sensing in single ended DRAM arrays. According to one embodiment of the present invention, a respective local sense amplifier compares the accessed memory cell data with a dummy cell data in the opposite or adjacent block of the accessed block that is connected to a respective local bit line in the opposite block, amplifies the result of the comparison and puts the data on a global bit line. In one embodiment, the invention is process and temperature invariant using reference method and means for canceling cross coupling between read lines and write lines.

    摘要翻译： 本发明描述了在单端DRAM阵列中差分感测的有效实现。 根据本发明的一个实施例，相应的本地读出放大器将访问的存储器单元数据与连接到相对块中的相应局部位线的相邻或相邻块中的虚拟单元数据进行比较，放大 比较结果并将数据放在全局位线上。 在一个实施例中，本发明是使用参考方法的工艺和温度不变量，以及用于消除读取线和写入线之间的交叉耦合的装置。

    Non-volatile electrically alterable semiconductor memory
    68.
    发明公开
    Non-volatile electrically alterable semiconductor memory 有权
    NichtflüchtigerelektrischveränderbarerHalbleiterspeicher

    公开(公告)号：EP1227499A1

    公开(公告)日：2002-07-31

    申请号：EP01830039.2

    申请日：2001-01-24

    申请人： STMicroelectronics S.r.l.

    发明人： Pio, Federico ,  Gomiero, Enrico

    IPC分类号： G11C16/08 ,  G11C7/18

    CPC分类号： G11C16/08 ,  G11C7/18

    摘要： Non-volatile, electrically alterable semiconductor memory, comprising at least one two-dimensional array of memory cells with a plurality of rows (R0-R511) and a plurality of columns (C(0;0)-C(127;31)), column selection means (CADD,3;CADD,10,INT_CADD,3) for selecting columns among said plurality of columns, and a write circuit (7) for simultaneously writing a first number of memory cells. A plurality of doped semiconductor regions (40-4127) is provided, extending transversally to the rows and subdividing a set of memory cells of each row in a corresponding plurality of subsets of memory cells, each subset of memory cells including memory cells of the row formed in a respective doped semiconductor region distinct from the remaining doped semiconductor regions and defining an elementary memory block (P) that can be individually erased. The plurality of doped semiconductor regions define a plurality of column packets (C(0;0)-C(0;31),...,C(127;0)-C(127;31)) each one containing a second number of columns equal to or higher than said first number, memory cells (MC) belonging to columns of a same column packet being formed in a same doped semiconductor region distinct from the doped semiconductor regions in which memory cells belonging to columns of the other column packets are formed. The column selection means are such that within each column packet columns containing memory cells that can be written simultaneously by the write circuit are distributed among the columns of the column packet so as to be at the substantially maximum distance from each other allowable within the column packet.

    摘要翻译： 包括具有多行（R0-R511）和多列（C（0; 0）-C（127; 31））的存储器单元的至少一个二维阵列的非易失性，电可更改的半导体存储器， 用于选择所述多个列中的列的列选择装置（CADD，3; CADD，10，INT_CADD，3）和用于同时写入第一数量的存储单元的写电路（7）。 提供了多个掺杂半导体区域（40-4127），其横向延伸到行并且在对应的多个存储器单元子集中细分每一行的一组存储器单元，每个存储单元子集包括行的存储单元 形成在与剩余的掺杂半导体区域不同的相应的掺杂半导体区域中，并且限定可被单独擦除的基本存储块（P）。 多个掺杂半导体区域限定多个列分组（C（0; 0）-C（0; 31），...，C（127; 0）-C（127; 31）） 等于或高于所述第一数量的列数，属于相同列分组的列的存储单元（MC）形成在与掺杂半导体区域不同的掺杂半导体区域中，其中属于另一列的列的存储单元 数据包被形成。 列选择装置使得在每列列中，包含可由写电路同时写入的存储单元的列被分布在列分组的列之间，以便在列分组内可允许的彼此基本上最大距离 。

    MEMORY DEVICE WITH INTERPLANE PAD PART
    69.
    发明公开
    MEMORY DEVICE WITH INTERPLANE PAD PART 审中-公开

    公开(公告)号：EP4447049A1

    公开(公告)日：2024-10-16

    申请号：EP24157343.5

    申请日：2024-02-13

    申请人： Samsung Electronics Co., Ltd.

    发明人： LEE, Myunghun ,  SHIN, Homoon

    IPC分类号： G11C5/02 ,  G11C7/18 ,  H10B41/20 ,  H10B41/40

    摘要： A memory device may include a first structure (ST1) and a second structure (ST2) bonded to the first structure (ST1). The first structure (ST1) may have a plurality of planes (PL1-PL6) and a pad part (PDP; PDP1, PDP2) between two planes adjacent to each other among the plurality of planes (PL1-PL6). Each of the plurality of planes (PL1-PL6) may include a memory cell. The second structure (ST2) may include a peripheral circuit. The plurality of planes (PL1-PL6) may be minimum units in which operations are independently performed and may be in an n x m array (n and m being integers of 2 or larger). The pad part (PDP; PDP1, PDP2) may be between the rows and/or between the columns of the n x m array.