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    SHAPING CODES FOR MEMORY
    83.
    发明公开
    SHAPING CODES FOR MEMORY 审中-公开
    记忆的形状代码

    公开(公告)号：EP2923270A1

    公开(公告)日：2015-09-30

    申请号：EP13856826.6

    申请日：2013-11-15

    Applicant: Micron Technology, Inc.

    Inventor： VARANASI, Chandra C.

    IPC: G06F12/00

    CPC classification number: G06F11/1072 ,  G06F11/10 ,  G06F11/1012 ,  G06F11/1016 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/10 ,  G11C29/04 ,  G11C29/50016 ,  G11C2029/5002

    Abstract: Apparatuses and methods associated with shaping codes for memory are provided. One example apparatus comprises an array of memory cells and a shaping component coupled to the array and configured to encode each of a number of received digit patterns according to a mapping of received digit patterns to shaping digit patterns. The mapping of received digit patterns to shaping digit patterns obeys a shaping constraint that limits, to an uppermost amount, an amount of consecutive digits of the shaping digit patterns allowed to have a particular digit value.

    Abstract translation: 提供了与整形用于存储器的代码相关联的设备和方法。 一个示例装置包括存储器单元阵列和耦合到阵列并且被配置为根据接收到的数字图案到成形数字图案的映射对多个接收到的数字图案中的每一个进行编码的整形部件。 接收到的数字模式到成形数字模式的映射服从成形约束，该成形约束将允许具有特定数字值的成形数字模式的连续数字的数量限制到最高数量。

    DRAM refresh frequency determination
    84.
    发明公开
    DRAM refresh frequency determination 审中-公开
    确定DRAM复习的频率

    公开(公告)号：EP2772919A3

    公开(公告)日：2015-06-17

    申请号：EP14160747.3

    申请日：2011-12-12

    Applicant: Qualcomm Incorporated

    Inventor： Suh, Jungwon

    IPC: G11C11/406 ,  G11C29/44 ,  G11C29/50

    CPC classification number: G11C11/40615 ,  G11C11/40626 ,  G11C29/50016 ,  G11C2029/4402 ,  G11C2211/4062

    Abstract: The invention concerns a method for determining a frequency for performing self-refresh and self-correction operations in a Dynamic Random Access Memory, DRAM, array. The method comprises measuring an operating temperature; determining an optimal frequency that minimizes the number of errors detected by an error correcting code, ECC, decoder based on the measured operating temperature; and setting the frequency for performing self-refresh and self-correction operations at the determined optimal frequency.

    MEMORY WITH REDUNDANT SENSE AMPLIFIER
    85.
    发明公开
    MEMORY WITH REDUNDANT SENSE AMPLIFIER 审中-公开
    SPEICHER MIT EINEM REDUNDANTENERFASSUNGSVERSTÄRKER

    公开(公告)号：EP2834817A1

    公开(公告)日：2015-02-11

    申请号：EP13717609.5

    申请日：2013-03-25

    Applicant: Apple Inc.

    Inventor： SENINGEN, Michael R. ,  RUNAS, Michael E.

    IPC: G11C29/12 ,  G11C29/50

    CPC classification number: G11C11/418 ,  G11C7/06 ,  G11C7/1051 ,  G11C29/1201 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/1204 ,  G11C2029/5002

    Abstract: Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.

    Abstract translation: 公开了一种存储器的实施例，其可以在读取弱数据存储单元时降低读取错误的可能性。 存储器可以包括多个数据存储单元，列多路复用器，第一读出放大器和第二读出放大器以及输出电路。 第一读出放大器的增益电平可以高于第二读出放大器的增益电平。 输出电路可以包括多路复用器，并且多路复用器可以可操作地可控地选择第一和第二读出放大器的输出之一并传递所选择的读出放大器的值。 输出电路可以包括耦合第一和第二读出放大器的输出的节点，并且第一和第二读出放大器的输出能够被设置为高阻抗状态。

    A METHOD OF TESTING DATA RETENTION OF A NON-VOLATILE MEMORY CELL HAVING A FLOATING GATE
    86.
    发明公开
    A METHOD OF TESTING DATA RETENTION OF A NON-VOLATILE MEMORY CELL HAVING A FLOATING GATE 有权
    程序对于非挥发性记忆体单元与浮栅数据保留

    公开(公告)号：EP2777065A1

    公开(公告)日：2014-09-17

    申请号：EP12848380.7

    申请日：2012-10-22

    Applicant: Silicon Storage Technology Inc.

    Inventor： MARKOV, Viktor ,  YOO, Jong-won ,  BANSAL, Satish ,  KOTOV, Alexander

    IPC: H01L21/02

    CPC classification number: G11C29/50 ,  G11C16/00 ,  G11C16/349 ,  G11C29/06 ,  G11C29/50004 ,  G11C29/50016

    Abstract: A method of decreasing the test time to determine data retention of a memory cell having a floating gate for the storage of charges thereon to determine if the memory cell has a leakage current from the floating gate. The memory cell is characterized by the leakage current having a rate of leakage which is dependent upon the absolute value of the voltage of the floating gate. The memory cell is further characterized by a first erase voltage and a first programming voltage applied during normal operation, and a first read current detected during normal operation. The method applies a voltage greater than the first erase voltage to over erase the floating gate. The memory cell including the floating gate is subject to a single high temperature bake. The memory cell is then tested for data retention of the floating gate based on the single high temperature bake.

    DRAM refresh frequency determination
    87.
    发明公开
    DRAM refresh frequency determination 审中-公开
    Bestimmung der Auffrischungsfrequenz eines DRAM

    公开(公告)号：EP2772919A2

    公开(公告)日：2014-09-03

    申请号：EP14160747.3

    申请日：2011-12-12

    Applicant: Qualcomm Incorporated

    Inventor： Suh, Jungwon

    IPC: G11C11/406

    CPC classification number: G11C11/40615 ,  G11C11/40626 ,  G11C29/50016 ,  G11C2029/4402 ,  G11C2211/4062

    Abstract: The invention concerns a method for determining a frequency for performing self-refresh and self-correction operations in a Dynamic Random Access Memory, DRAM, array. The method comprises measuring an operating temperature; determining an optimal frequency that minimizes the number of errors detected by an error correcting code, ECC, decoder based on the measured operating temperature; and setting the frequency for performing self-refresh and self-correction operations at the determined optimal frequency.

    Abstract translation: 本发明涉及用于确定在动态随机存取存储器DRAM阵列中执行自刷新和自校正操作的频率的方法。 该方法包括测量工作温度; 基于所测量的工作温度，确定最小化由纠错码ECC解码器检测到的误差数量的最佳频率; 并且以所确定的最佳频率设置用于执行自刷新和自校正操作的频率。

    EMBEDDED DRAM HAVING LOW POWER SELF-CORRECTION CAPABILITY
    89.
    发明公开
    EMBEDDED DRAM HAVING LOW POWER SELF-CORRECTION CAPABILITY 有权
    具有自纠错能力嵌入式DRAM，低功耗

    公开(公告)号：EP2649619A1

    公开(公告)日：2013-10-16

    申请号：EP11813470.9

    申请日：2011-12-12

    Applicant: Qualcomm Incorporated

    Inventor： SUH, Jungwon

    IPC: G11C11/406

    CPC classification number: G11C11/40615 ,  G11C11/40626 ,  G11C29/50016 ,  G11C2029/4402 ,  G11C2211/4062

    Abstract: Apparatuses and methods for low power combined self-refresh and self-correction of a Dynamic Random Access Memory (DRAM) array. During a self-refresh cycle, a first portion of a first row of the DRAM array is accessed and analyzed for one or more errors, wherein a bit width of the first portion is less than a bit width of the first row. If one or more errors are detected, the one or more errors are corrected to form a corrected first portion. The corrected first portion is selectively written back to the first row. If no errors are detected in the first portion, a write back of the first portion to the first row is prevented.

    BIT-REPLACEMENT TECHNIQUE FOR DRAM ERROR CORRECTION
    90.
    发明公开
    BIT-REPLACEMENT TECHNIQUE FOR DRAM ERROR CORRECTION 审中-公开
    比特交换DRAM纠错

    公开(公告)号：EP2502234A2

    公开(公告)日：2012-09-26

    申请号：EP10832017.7

    申请日：2010-11-10

    Applicant: Rambus Inc.

    Inventor： WARE, Frederick A. ,  TSERN, Ely ,  VOGELSANG, Thomas

    IPC: G11C29/42 ,  G11C29/18 ,  G11C11/40 ,  G06F11/10

    CPC classification number: G11C29/50016 ,  G06F11/1064 ,  G11C11/401 ,  G11C29/808

    Abstract: The disclosed embodiments provide a dynamic memory device, comprising a set of dynamic memory cells and a set of replacement dynamic memory cells. The set of replacement dynamic memory cells includes data cells which contain replacement data bits for predetermined faulty cells in the set of dynamic memory cells, and address cells which contain address bits identifying the faulty cells, wherein each data cell is associated with a group of address cells that identify an associated faulty cell in the set of dynamic memory cells. The dynamic memory device also includes a remapping circuit, which remaps a faulty cell in the set of dynamic memory cells to an associated replacement cell in the set of replacement cells.

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