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公开(公告)号：EP0349033B1
公开(公告)日：1994-01-19
申请号：EP89201548.8
申请日：1989-06-14
申请人： TEKTRONIX INC.
CPC分类号： G11C19/287 , G11C27/04
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公开(公告)号：EP0569858A2
公开(公告)日：1993-11-18
申请号：EP93107377.9
申请日：1993-05-06
申请人： YOZAN INC. , SHARP KABUSHIKI KAISHA
发明人： Yamamoto, Makoto
CPC分类号： G11C11/5621 , G11C27/04 , G11C2211/5644
摘要： The present invention has an object to provide a memory device for realizing an analog memory or a multilevel memory easy to produce and of small scale circuit.
A memory device according to the present invention realizes the small scale cell by means of storing analog data by circulating data on a plural number of linear CCD arrays which store data by electrical charge, makes it possible to access in high speed by reading and writing data through cache memory which comprises a row address corresponding to CCD array, and by registering on an address register the address of the data in cache memory.摘要翻译： 本发明的目的是提供一种用于实现易于产生的模拟存储器或多电平存储器和小规模电路的存储器件。 根据本发明的存储器件通过在多个通过电荷存储数据的多个线性CCD阵列上循环数据来存储模拟数据来实现小尺寸单元，使得可以通过读取和写入数据高速访问 通过高速缓冲存储器，其包括对应于CCD阵列的行地址，并且通过在地址寄存器中登记高速缓冲存储器中的数据的地址。
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公开(公告)号：EP0566129A1
公开(公告)日：1993-10-20
申请号：EP93106168.3
申请日：1993-04-15
申请人： SONY CORPORATION
CPC分类号： G11C27/04 , G11C19/285
摘要： The present invention is directed to a charge transfer apparatus. A reset gate (RG) is formed of an N-channel MOSFET of depletion type in which a carrier concentration of a channel region is set in a range from 10¹⁵ to 5 x 10¹⁶ cm⁻³. Also, a circuit for generating a reset pulse that is supplied to the reset gate (RG) is constructed as follows. A drain voltage source (12) and a drain of a transistor (Tr) are connected via a junction (a), and two resistors (R1) and (R2) are connected in series between the anode of the drain voltage source (12) and the ground. A junction (b) between the resistors (R1) and (R2) and the reset gate (RG) are connected together via an input line (13) and a high resistance (Rh) is inserted into the input line (13). Further, a coupling capacitor (Cc) is connected between a clock pulse input terminal (φin) and the input line (13). Thus, an amount that a potential formed under the reset gate is fluctuated by a fluctuation of an amount of implanted impurities and a fluctuation of a drain voltage can be reduced and hence a stable reset operation can be carried out.
摘要翻译： 本发明涉及一种电荷转移装置。 复位栅极（RG）由耗尽型N沟道MOSFET形成，其中沟道区域的载流子浓度设定在10 5至5×10 6 cm的范围内 < - > <3>。 此外，用于产生提供给复位门（RG）的复位脉冲的电路被构造如下。 漏极电压源（12）和晶体管（Tr）的漏极经由结（a）连接，并且两个电阻器（R1）和（R2）串联连接在漏极电压源（12）的阳极之间， 和地面。 电阻器（R1）和（R2）与复位栅极（RG）之间的结（b）通过输入线（13）连接在一起，高电阻（Rh）插入输入线（13）。 此外，耦合电容器（Cc）连接在时钟脉冲输入端（phi in）和输入线（13）之间。 因此，可以减少在复位栅极下形成的电位的波动，并且可以减少注入杂质的量的波动和漏极电压的波动，从而可以进行稳定的复位操作。
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84.发明公开Sampling device for sampling analog signals and digital measuring instrument provided with such a sampling device 失效采样装置，用于模拟信号和数字测量仪器，这种扫描装置的取样。
公开(公告)号：EP0540105A2
公开(公告)日：1993-05-05
申请号：EP92203270.1
申请日：1992-10-23
申请人： FLUKE CORPORATION
IPC分类号： G11C27/04
CPC分类号： G11C27/04
摘要： A sampling device (12) for a digital measuring instrument (1) is provided, which device (12) operates on the basis of time conversion. Compared with known sampling devices with time conversion based on CCD technology, the sampling device according to the invention comprises a retiming switch (d1) for retiming analog signals followed by a charge demultiplexing circuit (dmx) which operates in the charge domain. The charge demultiplexing circuit (dmx) is followed by a CCD array (pch0 to pch7) for storage of charge packages of the signal to be converted. The CCD structure, which is filled with charge packages at high speed, is read out at a much lower speed. The CCD structure according to the invention is optimally utilized through a suitable choice of control signals and is easy to control. Furthermore, less high requirements are set for the CCD drivers ad the peripheral clock system.
摘要翻译： 的取样装置（12），用于数字测量仪器（1）被提供，该装置（12）操作时间转换的基础上。 与基于CCD技术时间转换的已知采样装置相比，取样装置gemäß到本发明包括用于再定时随后分批多路分解电路（DMX）中的电荷域其操作的模拟信号重新定时开关（D1）。 将批料多路分解电路（DMX）由CCD阵列（pch0到pch7）为的信号电荷的包存储要转换其次。 填充有在高速充电包CCD结构，所有，是在低得多的速度被读出。 的CCD结构雅丁的发明是通过控制信号的适当选择可利用的OPTI马利和易于控制。 此外更多，更少高的要求的驱动CCD广告外设时钟系统设置。
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公开(公告)号：EP0289191B1
公开(公告)日：1992-12-23
申请号：EP88303509.9
申请日：1988-04-19
发明人： Hashimoto, Seiji
CPC分类号： G11C27/04 , G11C19/38 , H04N5/3692 , H04N5/376
摘要： A signal reading circuit for reading out a signal (on Ct) as a voltage to a signal line through a read transistor (QS) and for outputting is provided. This circuit has a selecting circuit (103) to select and output the signal on the signal line (101) after the read transistor was turned on or off.
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公开(公告)号：EP0458407A3
公开(公告)日：1992-09-09
申请号：EP91201192.1
申请日：1991-05-17
IPC分类号： G11C27/04
CPC分类号： G11C27/04
摘要： If charge is inputted to a charge coupled device by the so-called phase-referred input method a minority charge carrier source region (10) in a semiconductor body (1) is clocked in phase with a charge transfer gate (6) so that a metering potential well formed under a metering electrode (4) is alternately filled via a d.c. gate (5) with carriers to a predetermined level and then surplus carriers are drained back via the d.c. gate and the remainder exit via the transfer gate. This mechanism tends to degrade at high frequencies and, in order to improve the high frequency performance a very short further gate (20) is provided between the d.c. gate and the metering well. This further gate is clocked in antiphase to the source region (10) and the transfer gate (6) so that it creates a rising potential barrier when the surplus carriers are being drained back, isolating the metering well from the source (10) and the d.c. gate comparatively early in the complete draining process which would otherwise occur.
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公开(公告)号：EP0481531A2
公开(公告)日：1992-04-22
申请号：EP91120975.7
申请日：1988-05-20
CPC分类号： G11C27/04 , G11C19/285 , H01L29/76816
摘要： A charge transfer device comprises a floating diffusion region (50), a drain region (52) for discharging unnecessary charges when receiving a reset voltage (OR), and a reset gate electrode (53) for controlling the discharge of the stored charges of said floating diffusion region (50) into said drain region (52) according to a reset pulse, said floating diffusion region (50), drain region (52) and reset gate electrode (53) forming a first MOS transistor as a whole. A first voltage step-up means (11) steps up a predetermined voltage to provide a stepped-up voltage; and a reference voltage generating means (12, 14; 12, 22, 32; 161, 162) connected to said first voltage step-up means (11), includes a second MOS transistor (12, 161) substantially identical to said first MOS transistor, the second MOS transistor (12, 161) having a control terminal connected to a predetermined potential, a first current terminal connected to the stepped-up voltage of said first voltage step-up means (11), and a second current terminal connected to a predetermined potential through an electric element (14; 22, 32, 162). The reference voltage generating means (12, 14; 12, 22, 32; 161, 162) generates at said second current terminal of the second MOS transistor (12, 161) a voltage amounting to a potential lower by a predetermined potential "α" than a potential under said reset gate electrode (53) formed when the stored charges of said floating diffusion region (50) are discharged into said drain region (52). Second voltage step-up means (20; 33, 20) connected to said reference voltage generating means (12, 14; 12, 22, 32; 161, 162) and said drain region, step up the output voltage of said reference voltage generating circuit, and supply the stepped-up voltage as said reset voltage to said drain voltage (53).
摘要翻译： 电荷转移装置包括浮动扩散区（50），用于在接收复位电压（OR）时用于放电不必要电荷的漏极区域（52）），以及复位栅极电极（53），用于控制所述存储电荷 浮动扩散区域（50）根据复位脉冲进入所述漏极区域（52），所述浮动扩散区域（50），漏极区域（52）和复位栅电极（53）整体形成第一MOS晶体管。 第一升压装置（11）升高预定电压以提供升压电压; 和连接到所述第一升压装置（11）的基准电压产生装置（12,14; 12,22,32; 161,162）包括与所述第一MOS晶体管基本相同的第二MOS晶体管（12,161） 晶体管，具有连接到预定电位的控制端子的第二MOS晶体管（12,161），连接到所述第一升压装置（11）的升压电压的第一电流端子和连接到所述第一升压装置 通过电气元件（14; 22,32,162）到达预定电位。 参考电压产生装置（12,14; 12,22,32; 161,162）在第二MOS晶体管（12,161）的所述第二电流端产生一个电压，该电压下降到预定电位“α” 比当所述浮动扩散区域（50）的存储的电荷被排放到所述漏极区域（52）中时形成的所述复位栅电极（53）之下的电位低。 连接到所述参考电压发生装置（12,14; 12,22,32; 161,162）和所述漏极区的第二升压装置（20; 33,20），升高所述参考电压产生的输出电压 并且将升压电压作为所述复位电压提供给所述漏极电压（53）。
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88.发明公开Floating diffusion type charge detection circuit for use in charge transfer device 失效用于充电传输装置的浮动扩散型充电检测电路
公开(公告)号：EP0457270A3
公开(公告)日：1992-01-08
申请号：EP91107783.2
申请日：1991-05-14
申请人： NEC CORPORATION
CPC分类号： G11C27/04 , G11C19/285
摘要： A floating diffusion type signal charge detection circuit for use in a charge transfer device includes a charge transfer region formed in a semiconductor layer, a plurality of transfer electrodes formed on the charge transfer region through an insulating layer, a floating diffusion formed in the semiconductor layer adjacent to a final stage of the charge transfer region, a reset drain formed in the semiconductor layer separate from the floating diffusion and connected to a reset drain voltage, and a reset gate formed through an insulating layer on a portion of the semiconductor layer between the floating diffusion and the reset drain. The floating diffusion, the reset drain and the reset gate forms a reset transistor. An amplifier is connected at its input to the floating diffusion so as to detect a voltage change appearing in the floating diffusion. The amplifier includes a first amplification stage having a first MOS transistor having a gate connected to the floating diffusion and a drain connected to a high voltage, a source of the first MOS transistor being connected to a first load so that a first source follower is formed, and a second amplification stage having an input connected to the source of the first MOS transistor and an output node connected to an output terminal. An output control circuit is connected to the first MOS transistor and controlled in synchronism with a reset pulse applied to the reset gate so that when the reset transistor is off, the first source follower outputs an signal having a level higher than that outputted from the first source follower when the reset transistor were on.
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公开(公告)号：EP0394017A3
公开(公告)日：1991-06-12
申请号：EP90304160.6
申请日：1990-04-18
申请人： SONY CORPORATION
发明人： Narabu, Tadakuni, C/o. Sony Corporation , Kondo, Tetsuya, C/o. Sony Corporation , Maki, Yasuhito, C/o. Sony Corporation , Noguchi, Katsunori, C/o. Sony Corporation
CPC分类号： G11C27/04 , G11C19/285
摘要： An input structure of CCD comprises a primary register having an input gate and a source region and an automatic biasing system which generates a feedback signal to be fed back to input of the primary register. The output of the automatic biasing system is connected to one of the input gate and the source of the primary register for supplying the feedback signal thereto for adjusting input bias level of the primary register. The other one of the input gate and the source is connected to an information signal input terminal to receive therefrom an information signal to be transferred therethrough.
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公开(公告)号：EP0399832A2
公开(公告)日：1990-11-28
申请号：EP90305683.6
申请日：1990-05-24
发明人： Nishida, Yasuaki, c/o NHK Science and Tech. Res. , Matsunaga, Yoshiyuki, c/o Intellectual Prop. Div. , Harada, Nozomu, c/o Intellectual Prop. Div. , Manabe, Sohei, c/o Intellectual Prop. Div. , Endo, Yukio, c/o Intellectual Prop. Div.
CPC分类号： H04N5/335 , H01L27/14831 , H04N5/3765
摘要： A solid state image sensor comprises a CCD type image sensing device and a signal detector. This signal detector comprises an FDA type signal detection circuit (50) connected to a signal pick-up terminal of the image sensing device and having a small amount of saturating signals and low noise, an FDA type signal detection circuit (60) connected to the signal pick-up terminal and having a large amount of saturating signals and high noise, and a signal composing circuit (70) for composing the outputs of both signal detection circuits and outputting a composed output and changing a composing ratio in accordance with the output of the FDA type signal detection circuit (50).
摘要翻译： 固态图像传感器包括CCD型图像感测装置和信号检测器。 该信号检测器包括连接到图像感测装置的信号拾取端子并且具有少量饱和信号和低噪声的FDA型信号检测电路（50），连接到该信号检测电路 信号拾取端子，并且具有大量的饱和信号和高噪声;以及信号组合电路（70），用于组合两个信号检测电路的输出并输出组合输出，并根据输出 FDA类型信号检测电路（50）。
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