利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

143 条记录 (耗时 0.023 秒)

    CLOCK INSERTION DELAY SYSTEMS AND METHODS
    1.
    发明公开
    CLOCK INSERTION DELAY SYSTEMS AND METHODS 审中-公开

    公开(公告)号：EP4383573A1

    公开(公告)日：2024-06-12

    申请号：EP23213468.4

    申请日：2023-11-30

    申请人： Lattice Semiconductor Corporation

    发明人： SHAHBAZI, Maryam ,  SHARPE-GEISLER, Bradley A. ,  GUNARATNA, Senani ,  MCLAURY, Loren L.

    IPC分类号： H03K19/17736 ,  H03K19/17764

    CPC分类号： H03K19/17764 ,  H03K19/17744 ,  H03K19/1774

    摘要： Various techniques are provided to efficiently synchronize clock and data signals in programmable logic devices, PLDs. In one example, a method comprises configuring an intellectual property, IP, block of the PLD to receive a first clock signal and a first data signal at a first component of the IP block, determining a delay associated with the first clock signal between a first input and the first component, configuring a programmable logic cell, PLC, to receive a second clock signal and output the first data signal to the IP block, determining a delay period to synchronize the first clock signal and the first data signal at the first component of the IP block, and configuring an adjustable delay element to apply the delay period to the second clock signal to synchronize the first clock signal and the first data signal at the first component of the IP block. Additional systems and methods are also provided.

    FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
    4.
    发明公开
    FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES 审中-公开

    公开(公告)号：EP3506512A1

    公开(公告)日：2019-07-03

    申请号：EP18215835.2

    申请日：2018-12-24

    申请人： Lattice Semiconductor Corporation

    发明人： ZHANG, Fulong ,  HANDS, Gordon ,  SINGH, Satwant ,  HAN, Wei ,  LALL, Ravindar ,  COPLEN, Joel ,  HEGADE, Sreepada ,  DING, Ming Hui

    IPC分类号： H03K19/177

    摘要： Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD (200). The PLD includes an array of configuration memory cells including logic block memory cells (not shown with 225) and input/output (I/O) block memory cells (not shown with 205, 210, 215, 220) associated with the PLD's logic fabric (225) and I/O fabric (25, 210, 215, 220), respectively. The method further includes programming a subset of the I/O block memory cells (205, 210) with the configuration data, and providing a wakeup signal (245out) to activate functionality associated with a portion of the I/O fabric (205, 210). The method further includes programming remaining configuration memory cells of the array (215, 220, 225) with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells (215, 220). The method further includes providing a wakeup signal (245out) to activate functionality associated with at least a portion of the logic fabric (225). Related systems and devices (230) are provided.

    MULTI-TIME PROGRAMMABLE NON-VOLATILE MEMORY CELL
    7.
    发明公开
    MULTI-TIME PROGRAMMABLE NON-VOLATILE MEMORY CELL 审中-公开

    公开(公告)号：EP3345187A1

    公开(公告)日：2018-07-11

    申请号：EP16842708.6

    申请日：2016-08-26

    申请人： Lattice Semiconductor Corporation

    发明人： OMID-ZOHOOR, Farrokh Kia ,  BUI, Nguyen, Duc ,  LY, Binh

    IPC分类号： G11C17/16 ,  G11C17/18

    CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/11206 ,  H01L27/11582 ,  H01L28/00

    摘要： A non-volatile programmable bitcell has a read enable device with a source coupled with a bitline, an anti-fuse device with a gate coupled with a first write line, a drain coupled with a supply voltage and a source coupled with a drain of the read enable device. The bitcell has a fuse device coupled between a second write line and the drain of the read enable device. A magnitude of current flowing in the bitline, when the read enable device is enabled for reading, is dependent both on (1) a voltage level applied to the first write line and anti-fuse device state and on (2) a voltage level applied to the second write line and fuse device state. Usages include in a memory array, such as for FPGA configuration memory. The bitcell can be used as a multi-time programmable element, or to store multiple bit values.

    MAINTAINING SYNCHRONIZATION OF ENCRYPTION PROCESS ACROSS DEVICES BY SENDING FRAME NUMBERS
    8.
    发明公开
    MAINTAINING SYNCHRONIZATION OF ENCRYPTION PROCESS ACROSS DEVICES BY SENDING FRAME NUMBERS 审中-公开
    通过发送帧数维护设备间加密过程的同步

    公开(公告)号：EP3269139A1

    公开(公告)日：2018-01-17

    申请号：EP15884942.2

    申请日：2015-03-13

    申请人： Lattice Semiconductor Corporation

    发明人： WANG, Qingang ,  WANG, Hongpeng ,  CHOI, Hoon

    IPC分类号： H04N7/16

    CPC分类号： H04N21/4302 ,  G09G5/00 ,  G09G5/006 ,  G09G2358/00 ,  G09G2370/047 ,  G09G2370/12 ,  H04N21/4353 ,  H04N21/43635 ,  H04N21/4367

    摘要： Maintaining synchronization of encryption processes at devices during transmission of encrypted data over a communication link is provided. Cipher link maintenance characters are sent from a source device to a sink device. A local cipher link maintenance character generated at the sink device for decrypting the encrypted data can be adjusted according to the cipher link maintenance character. After authentication, cipher link maintenance characters corresponding to units (e.g., frames) of the encrypted data are sent along with the units of the encrypted data. When a transmission error occurs during transmission of the encrypted data, cipher link maintenance characters can be used to correct the error in a local cipher link maintenance character generated at the sink device. Hence, even if the transmission error occurs in the communication link, the sink device can resolve the transmission error and maintain the synchronization of encryption processes at the source and sink devices.