公开(公告)号：EP4439659A2

公开(公告)日：2024-10-02

申请号：EP24163723.0

申请日：2024-03-15

申请人： STMicroelectronics International N.V.

发明人： LUAN, Jing-En

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/538

CPC分类号： H01L23/49517 ,  H01L23/5389 ,  H01L21/568 ,  H01L21/561 ,  H01L23/49551

摘要： A hybrid QFN package includes an encapsulant body that encapsulates a lead frame and integrated circuit (IC) device where the lead frame includes a die pad and vertically offset leads. Back sides of the die pad and encapsulant body are coplanar at first surface. Front sides of the leads, the IC device and the encapsulant body are substantially coplanar at a second surface. An insulating layer covers the second surface except at a portion of the leads located at the peripheral edge of the encapsulating body. Vias extend through the insulating layer to the leads and IC device. Wiring lines on the insulating layer interconnect the vias. A passivation layer covers the wiring lines and vias.

公开(公告)号：EP3817033B1

公开(公告)日：2024-09-18

申请号：EP20204309.7

申请日：2020-10-28

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L23/49541 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49548 ,  H01L2224/7326520130101 ,  H01L2224/3224520130101 ,  H01L2224/4824720130101 ,  H01L2224/9720130101 ,  H01L2224/4809120130101 ,  H01L2924/181520130101 ,  H01L2924/18120130101

公开(公告)号：EP4415031A1

公开(公告)日：2024-08-14

申请号：EP23155542.6

申请日：2023-02-08

申请人： Infineon Technologies Austria AG

发明人： FUERGUT, Edward ,  MEYER, Thorsten ,  SCHOLZ, Wolfgang ,  ZUDOCK, Frank ,  ROTH, Alexander

IPC分类号： H01L21/56 ,  H01L23/00

CPC分类号： H01L24/49 ,  H01L21/4832 ,  H01L23/3107 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3735 ,  H01L23/4952

摘要： A method (100) for fabricating a semiconductor package comprises providing a die carrier (110), disposing a semiconductor die on the die carrier, the semiconductor die comprising one or more contact pads on a first main face thereof (120), applying an encapsulant at least partially to the semiconductor die, the encapsulant embedding at least one electrical connector, the electrical connector being connected with a contact pad or with the die carrier and extending to a main face of the encapsulant (130), and depositing at least one electrical layer onto the main face of the encapsulant and an exposed end of the at least one electrical connector (140).

公开(公告)号：EP2622635B1

公开(公告)日：2018-09-05

申请号：EP10857636.4

申请日：2010-09-29

申请人： Nexperia B.V.

发明人： LI, Martin, Ka Shing ,  LEUNG, Max ,  UMALI, Pompeo

IPC分类号： H01L21/56 ,  H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L21/683

CPC分类号： H01L21/78 ,  H01L21/4821 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/85

摘要： A method of dividing a two dimensional array of encapsulated integrated circuits into individual integrated circuit packages uses a first series of parallel cuts (32) extending fully through the leadframe (16) and encapsulation layer (14), and defining rows of the array. The cuts terminate before the beginning and end of the rows such that the integrity of the array is maintained by edge portions (34) at the ends of the rows. After plating contact pads (18), a second series of parallel cuts (36) is made extending fully through the leadframe (16) and encapsulation layer (14). This separates the array into columns thereby providing singulation of packages between the edge portions (34).

公开(公告)号：EP2543064B1

公开(公告)日：2018-08-01

申请号：EP10774342.9

申请日：2010-10-15

申请人： Xilinx, Inc.

发明人： RAHMAN, Arifur ,  MURALI, Venkatesan

IPC分类号： H01L25/065 ,  H01L21/98 ,  H01L21/60 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L21/82 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08137 ,  H01L2224/12105 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/2902 ,  H01L2224/29187 ,  H01L2224/30181 ,  H01L2224/30183 ,  H01L2224/32137 ,  H01L2224/73267 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/83005 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/145 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/83

摘要： An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.

公开(公告)号：EP3349240A1

公开(公告)日：2018-07-18

申请号：EP17208831.2

申请日：2017-12-20

申请人： Renesas Electronics Corporation

发明人： Yagyu, Yuki

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L21/561 ,  B29C45/0046 ,  B29C45/14655 ,  B29C45/14836 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48247 ,  H01L2224/49051 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2924/0105

摘要： A compact and high-reliability semiconductor device is implemented. The bonding wires situated in the vicinity of a gate, and the bonding wires situated in the vicinity of a vent facing to the gate across the center of a semiconductor chip in a molding step have a loop shape falling inwardly of the semiconductor chip, have a weaker pulling force (tension) than those of other bonding wires, and are loosely stretched with a margin. The bonding wires situated in the vicinity of the gate in the molding step are, for example, a first wire and a fifth wire to be connected with a first electrode pad and a fifth electrode pad, respectively. Whereas, the bonding wires situated in the vicinity of the vent in the molding step are, for example, a third wire and a seventh wire to be connected with a third electrode pad and a seventh electrode pad, respectively.

公开(公告)号：EP3064521B1

公开(公告)日：2018-07-11

申请号：EP14878027.3

申请日：2014-11-28

申请人： SHIN-ETSU CHEMICAL CO., LTD

发明人： SUMITA, Kazuaki ,  UEHARA, Tatsuya ,  KUSHIHARA, Naoyuki

IPC分类号： C08G59/42 ,  C08K9/06 ,  C08L63/00 ,  H01L23/29 ,  H01L23/31 ,  C08G59/32 ,  C08G59/68 ,  C08G59/24

CPC分类号： H01L21/561 ,  C08G59/245 ,  C08G59/3218 ,  C08G59/3227 ,  C08G59/3281 ,  C08G59/42 ,  C08G59/686 ,  C08K3/36 ,  C08K5/09 ,  C08K9/06 ,  C08K2201/003 ,  C08L63/00 ,  C09D7/62 ,  C09D7/63 ,  C09D163/00 ,  H01L21/78 ,  H01L23/296 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a liquid epoxy resin composition for semiconductor sealing, which contains: (A) a liquid epoxy resin that does not contain a siloxane bond in each molecule; (B) an acid anhydride-based curing agent; (C) a surface-treated spherical inorganic filler which is a spherical inorganic filler having an average particle diameter of 0.1-10 µm as determined by a laser diffraction method and serving as an inorganic filler, and wherein the surface of the spherical inorganic filler is surface-treated with 0.5-2.0 parts by weight of a (meth)acrylic functional silane coupling agent per 100 parts by weight of the spherical inorganic filler of the component (C); and (D) a curing accelerator. The present invention is able to provide a semiconductor device which has excellent heat resistance and moisture resistance.

公开(公告)号：EP3332419A1

公开(公告)日：2018-06-13

申请号：EP16751791.1

申请日：2016-08-05

申请人： Qorvo US, Inc.

发明人： COSTA, Julio C. ,  MORRIS, Thomas Scott ,  HAMMOND, Jonathan Hale ,  JANDZINSKI, David ,  PARKER, Stephen ,  CHADWICK, Jon

IPC分类号： H01L23/31 ,  H01L21/56

CPC分类号： H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L23/295 ,  H01L23/3135 ,  H01L23/4334 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19011 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014

摘要： A flip chip module having at least one flip chip die is disclosed. The flip chip module includes a carrier having a top surface with a first mold compound residing on the top surface. A first mold compound is disposed on the top surface of the carrier. A first thinned flip chip die resides over a first portion of the first mold compound with interconnects extending through the first portion to the top surface wherein the first portion of the mold compound fills a region between the first flip chip die and the top surface. A second mold compound resides over the substrate and provides a first recess over the first flip chip die wherein the first recess extends to a first die surface of the first flip chip die. A third mold compound resides in the first recess and covers an exposed surface of the flip chip die.

公开(公告)号：EP3172048A4

公开(公告)日：2018-04-18

申请号：EP14873107

申请日：2014-07-11

申请人： INTEL CORP

发明人： LEVANDER ALEJANDRO ,  ANDRYUSHCHENKO TATYANA ,  STAINES DAVID ,  KOBRINSKY MAURO ,  ALEKSOV ALEKSANDAR ,  SENEVIRATNE DILAN ,  SOTO GONZALEZ JAVIER ,  PIETAMBARAM SRINIVAS ,  ISLAM RAFIQUL

IPC分类号： B32B27/08 ,  B23B5/16 ,  H01L21/20 ,  H05K1/00

CPC分类号： H01L23/4985 ,  B23B5/16 ,  B32B27/08 ,  B32B27/283 ,  B32B2307/54 ,  B32B2307/7265 ,  B32B2439/00 ,  B32B2457/00 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/85 ,  H01L24/96 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/48227 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0715 ,  H01L2924/15747 ,  H01L2924/15791 ,  H05K1/0283 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.

公开(公告)号：EP3298625A1

公开(公告)日：2018-03-28

申请号：EP16728156.7

申请日：2016-05-19

申请人： Qualcomm Incorporated

发明人： RAE, David Fraser ,  KESER, Lizabeth Ann ,  ALVARADO, Reynante Tamunan

IPC分类号： H01L21/60 ,  H01L25/16 ,  H01L23/538 ,  H01L25/10 ,  H01L21/56

CPC分类号： H01L21/768 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/81

摘要： A package may include a die proximate to a structure having a substrate with interconnects and a first component coupled to the interconnects. The die may be face up or face down. The package may include a first redistribution layer coupling the die to the interconnects of the structure and a mold compound covering the die and maybe the structure.