公开(公告)号：EP4439659A2

公开(公告)日：2024-10-02

申请号：EP24163723.0

申请日：2024-03-15

申请人： STMicroelectronics International N.V.

发明人： LUAN, Jing-En

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/538

CPC分类号： H01L23/49517 ,  H01L23/5389 ,  H01L21/568 ,  H01L21/561 ,  H01L23/49551

摘要： A hybrid QFN package includes an encapsulant body that encapsulates a lead frame and integrated circuit (IC) device where the lead frame includes a die pad and vertically offset leads. Back sides of the die pad and encapsulant body are coplanar at first surface. Front sides of the leads, the IC device and the encapsulant body are substantially coplanar at a second surface. An insulating layer covers the second surface except at a portion of the leads located at the peripheral edge of the encapsulating body. Vias extend through the insulating layer to the leads and IC device. Wiring lines on the insulating layer interconnect the vias. A passivation layer covers the wiring lines and vias.

公开(公告)号：EP4439634A2

公开(公告)日：2024-10-02

申请号：EP24194383.6

申请日：2016-07-28

申请人： QUALCOMM Incorporated

发明人： WE, Hong Bok ,  LEE, Jae Sik ,  KIM, Dong Wook ,  GU, Shiqun

IPC分类号： H01L21/56

CPC分类号： H01L23/13 ,  H01L23/49816 ,  H01L21/4846 ,  H01L23/5389 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/040120130101 ,  H01L2224/0410520130101 ,  H01L2224/13120130101 ,  H01L2224/1622720130101 ,  H01L2224/1623720130101 ,  H01L2224/7320420130101 ,  H01L2224/8181520130101 ,  H01L2924/1433520130101 ,  H01L2924/1531120130101 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2224/1210520130101 ,  H01L2924/143420130101 ,  H01L2924/143220130101 ,  H01L2224/9620130101

摘要： A package-on-package (POP) structure is disclosed. The POP structure includes a first die, a second die, and a photo-imaged dielectric (PID) layer. The PID layer is disposed between the first die and the second die. The POP structure also includes a first conductive path from the first die through the PID layer to the second die. The first conductive path extends directly through a first area of the PID layer directly between the first die and the second die. The POP structure further includes a second conductive path from the first die through the PID layer to the second die. A particular portion of the second conductive path is perpendicular to the first conductive path and extends through a second area of the PID layer not directly between the first die and the second die.

公开(公告)号：EP3547362B1

公开(公告)日：2024-08-21

申请号：EP19160265.5

申请日：2019-03-01

IPC分类号： H01L23/66 ,  H01L23/31 ,  H01L23/00 ,  H01Q1/22 ,  H01Q21/06 ,  H01Q21/28 ,  H01L23/538 ,  H01Q9/04 ,  H01P5/16

CPC分类号： H01L23/3171 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L24/96 ,  H01L2223/667720130101 ,  H01L2224/0410520130101 ,  H01L2224/1210520130101 ,  H01L2924/1816220130101 ,  H01L2224/1413320130101 ,  H01L2224/1622520130101 ,  H01L2224/1310120130101 ,  H01L24/13 ,  H01Q1/2283 ,  H01Q21/28 ,  H01Q9/0407 ,  H01Q21/065 ,  H01P5/16 ,  H01L2223/662720130101 ,  H01L2224/7320920130101 ,  H01L2224/7310420130101 ,  H01L2224/1308220130101

公开(公告)号：EP4388386A1

公开(公告)日：2024-06-26

申请号：EP22769435.3

申请日：2022-08-16

申请人： Tesla, Inc.

发明人： SUN, Shishuang ,  VENKATARAMANAN, Ganesh ,  SUN, Yang ,  ZHAO, Jin ,  DENG, Shaowei ,  CHANG, William ,  PANG, Mengzhi ,  BUTLER, Steven ,  MCGEE, William Arthur ,  NABOVATI, Aydin

IPC分类号： G06F1/20

CPC分类号： G06F1/20 ,  G06F2200/20120130101 ,  H01L23/473 ,  H05K7/20772 ,  H01L23/5389 ,  H01L2225/0658920130101 ,  H01L25/0652 ,  H01L25/18

公开(公告)号：EP4383325A1

公开(公告)日：2024-06-12

申请号：EP23212555.9

申请日：2023-11-28

申请人： NXP USA, Inc.

发明人： Hayes, Scott M ,  Huang, Wen Hung ,  VINCENT, Michael B ,  Kamphuis, Antonius Hendrikus Jozef ,  Gong, Zhiwei ,  van Gemert, Leo

IPC分类号： H01L23/00 ,  H01L23/538

CPC分类号： H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/20 ,  H01L24/23 ,  H01L2924/18120130101 ,  H01L2224/2422120130101 ,  H01L2225/0654820130101 ,  H01L2224/3214520130101 ,  H01L2225/0651720130101 ,  H01L2225/0655820130101 ,  H01L25/0657 ,  H01L25/0652 ,  H01L25/50 ,  H01L23/49816 ,  H01L2225/0658620130101

摘要： An electronic device package and method of fabricating such a package includes a first and second components encapsulated in a volume of molding material. A surface of the first component is bonded to a surface of the second component. Upper and lower sets of redistribution lowers that include, respectively, first and second sets of conductive interconnects are formed on opposite sides of the molding material. A through-package interconnect passes through the volume of molding material and has ends that terminate, respectively, within the upper set of redistribution layers and within the lower set of redistribution layers.

公开(公告)号：EP3840114B1

公开(公告)日：2024-05-29

申请号：EP20212279.2

申请日：2020-12-07

IPC分类号： H01Q1/22 ,  H01Q13/06 ,  H01Q21/06 ,  H01Q21/00 ,  G01S7/03 ,  H01L23/13 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  G01S13/931 ,  H01L23/498

CPC分类号： H01Q1/2283 ,  H01Q13/06 ,  H01Q21/064 ,  H01Q21/0087 ,  H01L23/66 ,  H01L2223/667720130101 ,  G01S7/032 ,  H01L23/5389 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  G01S13/931 ,  H01L2223/662720130101 ,  H01L2224/2419520130101 ,  H01L2224/1210520130101 ,  H01L24/19 ,  H01L24/20 ,  H01L2924/1816220130101

公开(公告)号：EP4362078A1

公开(公告)日：2024-05-01

申请号：EP23193888.7

申请日：2023-08-29

申请人： Intel Corporation

发明人： ECTON, Jeremy ,  MARIN, Brandon C. ,  PIETAMBARAM, Srinivas ,  DUAN, Gang ,  NAD, Suddhasattwa

IPC分类号： H01L23/15 ,  H01L23/00

CPC分类号： H01L24/19 ,  H01L24/20 ,  H01L23/15 ,  H01L23/5389

摘要： Multi-die packages including a glass substrate within a space between adjacent IC dies. Two or more IC die may be placed within recesses formed in a glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. Organic package dielectric material may then be built up on both sides of the IC dies and glass substrate. Metallization features formed within package dielectric material built up on a first side of the IC die may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects. Metallization features formed within package dielectric material built up on a second side of the first and second IC dies may electrically interconnect the first IC die to the second IC die.

公开(公告)号：EP4350766A3

公开(公告)日：2024-04-17

申请号：EP23198932.8

申请日：2023-09-21

申请人： Huawei Digital Power Technologies Co., Ltd.

发明人： ZHAO, Chunyan ,  SHEN, Chao ,  BAO, Kuanming

IPC分类号： H01L23/538

CPC分类号： H01L23/5383 ,  H05K1/0233 ,  H05K2201/100620130101 ,  H05K2201/100320130101 ,  H05K1/186 ,  H01L23/36 ,  H01L23/5389 ,  H01L23/50 ,  H01L25/16

摘要： This application provides an embedded package structure, a power supply apparatus, and an electronic device. First electronic components with smaller sizes are stacked, and then arranged in a substrate frame in a two-dimensional manner with a larger-size inductor component to form an embedded package structure. This can reduce an area occupied by the entire embedded package structure, and reduce an overall size of the structure, thereby facilitating integration and miniaturization. Then, a chip is disposed on the embedded package structure, so that the chip serving as a main heat source is placed on a surface of the power supply apparatus. Compared with an existing power module structure in which a chip is embedded in a substrate to form an ECP module and an inductor is mounted on a surface of the ECP module, in the embedded package structure provided in this application, a main heat dissipation path of the chip is changed from an existing downward heat dissipation direction to an upward heat dissipation direction, which may improve a heat dissipation capability.

公开(公告)号：EP3364456A2

公开(公告)日：2018-08-22

申请号：EP17210055.4

申请日：2017-12-22

申请人： At&S (China) Co., Ltd.

发明人： Tuominen, Mikael ,  Tay, Annie ,  Baftiri, Artan

IPC分类号： H01L23/538 ,  H05K1/18 ,  H05K1/02

CPC分类号： H05K1/185 ,  C09J7/00 ,  C09J2201/626 ,  C09J2203/326 ,  H01L23/5389 ,  H05K1/0204 ,  H05K3/4652 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2201/10416 ,  H05K2201/2072 ,  H05K2201/209 ,  H05K2203/0191 ,  H05K2203/063

摘要： A method of using a sheet (100) with nano- and/or microstructures (102) on a sheet surface (104) for manufacturing a component carrier (106).

公开(公告)号：EP3306651A3

公开(公告)日：2018-08-15

申请号：EP17195021.5

申请日：2017-10-05

申请人： MediaTek Inc.

发明人： CHEN, Nan-Cheng ,  CHOU, Che-Ya ,  LIU, Hsing-Chih ,  KUO, Che-Hung

IPC分类号： H01L21/60 ,  H01L23/14 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/31 ,  H01L23/145 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor device includes a substrate (110), a body structure (120) and an electronic component (130). The body structure is disposed above the substrate and includes a semiconductor die (121), a molding compound (122), a conductive component (123) and a lower redistribution layer (RDL) (124). The semiconductor die has an active surface (121a). The molding compound encapsulates the semiconductor die and has a lower surface (122b), an upper surface (122u) opposite to the lower surface and a through hole (122h) extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.