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    PROGRAMMABLE MEMORY REPAIR SCHEME
    7.
    发明公开
    PROGRAMMABLE MEMORY REPAIR SCHEME 审中-公开
    REPARATURSCHEMAFÜRPROGRAMMIBAREN SPEICHER

    公开(公告)号：EP2301038A1

    公开(公告)日：2011-03-30

    申请号：EP09730954.6

    申请日：2009-04-09

    申请人： Rambus Inc.

    发明人： ONG, Adrian, E. ,  HO, Fan

    IPC分类号： G11C29/00

    CPC分类号： G11C29/76 ,  G11C11/401 ,  G11C11/4085 ,  G11C29/027 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/789 ,  G11C29/802 ,  G11C2229/743

    摘要： The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element.

    摘要翻译： 本公开提供了用于测试和操作该半导体器件的方法，系统和装置。 半导体存储器件包括数据存储元件和修复电路。 数据存储元件包括主数据存储元件和一个或多个冗余数据存储元件，主数据存储元件具有用于存储器访问操作的相应地址。 修复电路可以由与存储器件分离的另一个半导体器件编程，以识别主数据存储元件的故障地址，并且编程的修复电路被配置为将具有识别的故障地址的主数据存储元件的存储器访问重新路由到相应的 冗余数据存储元件。

    Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays
    8.
    发明公开
    Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays 审中-公开
    嵌入式存储器定制的可编程自检和自我修复装置

    公开(公告)号：EP1624465A1

    公开(公告)日：2006-02-08

    申请号：EP04425617.0

    申请日：2004-08-06

    申请人： STMicroelectronics S.r.l.

    发明人： Zappa, Rita ,  Selva, Carolina ,  Rimondi, Danilo ,  Torelli, Cosimo

    IPC分类号： G11C29/00

    CPC分类号： G11C29/16 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/72

    摘要： A built-in self-test and self-repair structure (BISR) of memory arrays embedded in an integrated device, including at least a test block (BIST) programmable to execute on a respective memory array of the device any of a certain number of predefined test algorithms, and a self-repair block that includes a column address generator processing the faulty addresses information for allocating redundant resources of the tested memory array, a redundancy register on which final redundancy information are loaded at each power-on of the device and a control logic for managing data transfer from external circuitry to the built-in self-test and self-repair structure (BISR) and vice versa, utilizes a single built-in self-test (BIST) structure serves any number of embedded memory arrays even of different type and size.
    The built-in self-test and self-repair (BISR) structure further includes nonvolatile storage means containing information on addresses and data bus sizes of the device architecture, aspect ratio, capacity, multiplexing and scrambling parameters and relative test algorithm instructions for each of said embedded memory arrays and on which redundance column addresses are permanently stored and a multiple frequency clock generator for selecting the maximum operating clock frequency of the type of embedded memory array to be accessed.
    Two distinct selectable test flows of an embedded random access memory array are selectable by programming. A first two-step test flow, each step of which includes the execution of a complete BIST check on the array, and a second three-step test flow, each step of which includes the execution of a complete BIST check on the array, the third BIST check revealing a possible failed programming of the redundance column addresses in said nonvolatile storage means.

    摘要翻译： 甲内建自测试，并在集成设备中的嵌入式存储器阵列中的自修复结构（BISR），包括至少一个测试块（BIST）可编程的，以执行设备的任何特定数量的的respectivement存储器阵列 预定义的测试算法和一个自修复块做了包括上电设备的列地址发生器处理，以分配测试存储器阵列，其上最终冗余信息在每个加载的冗余寄存器的冗余资源的故障地址的信息和 用于管理从外部电路的数据传送到控制逻辑内置自测试和自修复结构（BISR），反之亦然，利用单个内建自测试（BIST）结构用于任何数目的嵌入式存储器阵列的 甚至不同的类型和大小。 该内建自测试和自修复（BISR）结构还包括非易失性存储装置，包含对每个的地址和设备架构的数据总线大小，长宽比，容量，复用和扰频参数和相对测试算法的指令信息 所述嵌入的存储器阵列和在其冗余列地址永久地存储和被访问，用于选择嵌入式存储器阵列的类型的最大工作时钟频率的倍数的频率的时钟发生器。 嵌入式随机存取存储器阵列的两个不同的可选择的测试流是由编程选择。 第一两步测试流，每个步骤都包括在阵列上的完整BIST检查的执行，和一个第二三步测试流，每个步骤都包括一个完整的BIST检查阵列上执行，所述 第三BIST检查揭示在所述非易失性存储装置中的冗余列地址的一个可能的编程失败。