SYSTEM AND METHOD FOR ERROR CORRECTION IN A CORRELATION-BASED PITCH ESTIMATOR
    3.
    发明公开
    SYSTEM AND METHOD FOR ERROR CORRECTION IN A CORRELATION-BASED PITCH ESTIMATOR 失效
    用于纠错系统和方法来纠正基于离子基频估计设备

    公开(公告)号:EP0882287A1

    公开(公告)日:1998-12-09

    申请号:EP97904886.0

    申请日:1997-01-24

    IPC分类号: G10L25

    CPC分类号: G10L25/90 G10L25/06

    摘要: The present invention comprises an improved method for estimating and correcting the pitch parameter using correlation techniques. The method comprises first performing a correlation calculation on a frame of the speech waveform, which produces one or more correlation peaks at respective numbers of delay samples. The vocoder then compares the one or more correlation peaks with a clipping threshold value. If a single peak at location Pd is greater than the clipping threshold, then the vocoder perfoms additional calculations to ensure that this single correlation peak is not a second or higher multiple of the true pitch. In the preferred embodiment, the vocoder assumes the peak at location Pd is a second multiple of the true pitch, and the vocoder searches for the true pitch at a first multiple of the peak location Pd. If a peak is found at this first multiple, referred to as Pd', and certain other criteria are met, then the peak at location Pd' is presumed to be the true pitch. In this case, the pitch is set to the number of delay samples indicated by Pd'. Thus the present invention more accurately disregards false peaks which are second or higher multiples of the true pitch.

    CMOS CURRENT MIRROR
    4.
    发明公开
    CMOS CURRENT MIRROR 失效
    CMOS电动后视镜

    公开(公告)号:EP0880735A1

    公开(公告)日:1998-12-02

    申请号:EP96936674.0

    申请日:1996-10-17

    IPC分类号: G05F3

    CPC分类号: G05F3/262

    摘要: A current mirror circuit for mirroring current in CMOS integrated circuit technology includes a current mirror arrangement formed of first and second P-channel MOS transistors (MP32, MP33), a variable input current source (Ics), a first source follower transistor (MN34), a second source follower transistor (MP35), a current-sinking transistor (MN31), and a load circuit (212). The load circuit is formed of a load transistor (MN36) and a load resistor (R1). In an alternate embodiment, the load circuit is formed of a single load resistor. As a result, the amount of current injected into the first P-channel MOS transistor (MP32) is more precisely mirrored into the second P-channel MOS transistor (MP33).

    DTMF DETECTOR SYSTEM AND METHOD WHICH PERFORMS STATIC AND DYNAMIC THRESHOLDING
    5.
    发明公开
    DTMF DETECTOR SYSTEM AND METHOD WHICH PERFORMS STATIC AND DYNAMIC THRESHOLDING 失效
    ZWEITONMEHRFREQUENZDETEKTIONSSYSTEM和静力学和动力学阈值程序

    公开(公告)号:EP0872122A1

    公开(公告)日:1998-10-21

    申请号:EP97901443.0

    申请日:1997-01-10

    发明人: XIE, Zheng-yi

    IPC分类号: H04Q1

    CPC分类号: H04Q1/453 H04Q1/457

    摘要: An improved dual tone multifrequency (DTMF) or multitone signal detector which uses both static and dynamic thresholding techniques to provide an increased functional dynamic range, improved speech immunity for improved detection and reduced error, and simplified signal to noise ratio control. The DTMF detector receives signals from the transmission media, calculates energy values for the different frequencies, and then determines maximum values of the energy values for each of the frequency groups, referred to as M(1) and M(2). The DTMF detector then performs both static and dynamic thresholding according to the present invention to ensure valid tone detection. The static thresholding compares each of the M(1) and M(2) values with a static threshold value to ensure that the maximum energy values have a minimum energy to warrant detection. Since both static and dynamic thresholding are performed according to the present invention, the static threshold value is preferably set low, thus allowing an increased functional dynamic range. The dynamic thresholding computes the ratio of the maximum value in each sub-array to each of the other values in the respective sub-array, wherein the remaining values in the sub-array are presumed to be noise. This ratio essentially computes the signal to noise ratio (SNR) of the received signals. These ratios are then compared with a second threshold. If the maximum energies are not greater than the static threshold, or any of the ratios is not greater than the second threshold value, then a SNR error is set, and no detection is indicated. The present invention improves the DTMF detector's functional dynamic range and noise immunity.

    COMPUTER SYSTEM WHICH INCLUDES A LOCAL EXPANSION BUS AND A DEDICATED REAL-TIME BUS FOR INCREASED MULTIMEDIA PERFORMANCE
    6.
    发明公开
    COMPUTER SYSTEM WHICH INCLUDES A LOCAL EXPANSION BUS AND A DEDICATED REAL-TIME BUS FOR INCREASED MULTIMEDIA PERFORMANCE 失效
    WITH A扩展总线并且分配给增加的多媒体性能实时总线计算机系统

    公开(公告)号:EP0850450A1

    公开(公告)日:1998-07-01

    申请号:EP96921607.0

    申请日:1996-06-13

    IPC分类号: G06F13

    CPC分类号: G06F13/409

    摘要: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. The PCI bus and the multimedia bus are comprised on the motherboard and include connector slots for receiving add-in cards. Multimedia device expansion cards each include two connectors which correspond to the PCI bus and the multimedia bus. Thus multimedia devices such as video cards, audio cards, etc., as well as communications devices, transfer real-time data through a separate bus without requiring arbitration for the PCI bus. The computer suystem of the present invention thus provides much greater performance for real-time applications than prior systems.

    A DATA CACHE CONFIGURED TO STORE STACK DATA IN A STACK DATA STORAGE
    8.
    发明公开
    A DATA CACHE CONFIGURED TO STORE STACK DATA IN A STACK DATA STORAGE 失效
    具有集成堆栈缓存缓存

    公开(公告)号:EP0888587A1

    公开(公告)日:1999-01-07

    申请号:EP97904850.0

    申请日:1997-01-24

    发明人: LYNCH, Thomas, W.

    IPC分类号: G06F9 G06F12

    摘要: A data cache is provided which stores stack data within a stack memory separate from the cache line oriented storage used for non-cache data. Data may be pushed, popped, and accessed via an offset from the stack memory without generating main memory addresses. A load/store unit coupled to the data cache may be configured to perform the address generation associated with stack accesses in parallel with performing the access to the stack memory. If the corresponding data is not stored within the stack memory, then an access to the cache line oriented storage may be performed. Therefore, no time penalty may be assessed for missing the stack memory. A stack memory is contemplated for use with respect to subroutine parameter passing. The calling routine may perform multiple push commands to place parameters for use by the subroutine onto the stack. The subroutine may then access and modify the parameters upon the stack. Finally, the calling routine may perform multiple pop commands to remove the parameters from the stack.

    SYSTEM FOR RECONFIGURING THE WIDTH OF AN XYRAM
    9.
    发明公开
    SYSTEM FOR RECONFIGURING THE WIDTH OF AN XYRAM 失效
    系统重新配置的存储器的长度XYRAM

    公开(公告)号:EP0860010A1

    公开(公告)日:1998-08-26

    申请号:EP96936487.0

    申请日:1996-10-15

    IPC分类号: G11C7

    CPC分类号: G11C7/1006

    摘要: An x-y RAM array with a reconfigurable bit width is provided. The array contains a RAM cell columns organized into a number of column groups where the number of groups determines the bit width of the memory. The number of columns in each group are configurable thereby configuring the number of groups and thus the bit width of the memory. Multiplexor logic selects a column from each group to be accessed and passgate logic determines how the multiplexor logic is combined and thus determines the column group configuration. Decode logic provides the appropriate select signals to the multiplexor logic for selecting from the configured number of columns in each group.

    SELF-MODIFYING CODE HANDLING SYSTEM
    10.
    发明公开
    SELF-MODIFYING CODE HANDLING SYSTEM 失效
    系统进行处理代码自修改

    公开(公告)号:EP0853785A1

    公开(公告)日:1998-07-22

    申请号:EP96933906.0

    申请日:1996-10-03

    IPC分类号: G06F9

    摘要: A processor (100) which includes tags indicating memory addresses for instructions advancing through pipeline stages of the processor and which includes an instruction decoder (140) having a store target address buffer allows a self-modifying code handling system to detect store operations writing into the instruction stream and trigger a self-modifying code fault. In one embodiment of a self-modifying code handling system, a store pipe (153, 159) is coupled to a data cache (170) to commit results of a store operation to a memory subsystem (122). The store pipe supplies as store operation target address indication on commitment of a store operation result. A scheduler (180) includes ordered Op entries for Ops decoded from instructions and includes corresponding first address tags covering memory addresses for the instructions. First comparison logic (236) is coupled to the store pipe and to the first address tags to trigger self-modifying code fault handling means in response to a match between the store operation target address and one of the first address tags. An instruction decoder (140) is coupled between the instruction cache (130) and the scheduler (180). The instruction decoder includes instruction buffer entries and second address tags associated with the instruction buffer entries. Second comparison logic (444) is coupled to the store pipe and to the second address tags to trigger the self-modifying code fault handling means in response to a match between the store operation target address and one of the second address tags.