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公开(公告)号：EP4398309A1
公开(公告)日：2024-07-10
申请号：EP23220797.7
申请日：2023-12-29
发明人： ZHOU, Jifeng , ZHANG, Glenda , HE, Lei
IPC分类号： H01L29/06 , H01L29/08 , H01L29/747 , H01L29/423
CPC分类号： H01L29/747 , H01L29/0661 , H01L29/083 , H01L29/0696 , H01L29/42308
摘要： A TRIAC semiconductor includes an N- region (310), multiple N+ regions (314a-e), and a trench (326). The N- region (310) is sandwiched between two P regions (308, 312). The first P region (308) is connected to an MT2 terminal and the second P region (312) is connected to two MT1 terminals. The multiple N+ regions are located within the first P region (312). The trench (326) is located between two gate terminals (G).
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公开(公告)号：EP4383343A1
公开(公告)日：2024-06-12
申请号：EP23213794.3
申请日：2023-12-01
发明人： Zhou, Jifeng , Zhang, Glenda , He, Lei
IPC分类号： H01L29/10 , H01L29/744
CPC分类号： H01L29/102 , H01L29/744
摘要： A silicon controlled rectifier includes a first P region (308), an N- region (310), a second P region (312), and a plurality of N+ regions (314a-e, 328). The first P region is connected to an anode (302). The N- region is adjacent the first P region. The second P region is adjacent the N- region such that the N- region is sandwiched between the first P region and the second P region. The plurality of N+ regions are disposed within the second P region. A first N+ region (314a-e) of the plurality of N+ regions is connected to a cathode (304). A second N+ region (328) of the plurality of N+ regions is connected to a gate (306). The device has a low shunt-current.
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公开(公告)号：EP4362092A1
公开(公告)日：2024-05-01
申请号：EP23203710.1
申请日：2023-10-16
发明人： Zhang, Glenda , Shi, Lei , Gao, Chao
IPC分类号： H01L25/07
CPC分类号： H01L25/074 , H01L23/49844 , H01L23/49513 , H01L23/49537 , H01L23/49575
摘要： A multiple-channel protection device and associated methods thereof. The device includes a first lead having a first chip attachment portion and a second chip attachment portion, a second lead having a third chip attachment portion, and a third lead having a fourth chip attachment portion. A first semiconductor chip is configured to be conductively coupled to the first chip attachment portion and the third chip attachment portion. A second semiconductor chip is configured to be conductively coupled to the second chip attachment portion and the fourth chip attachment portion.
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公开(公告)号：EP4362085A1
公开(公告)日：2024-05-01
申请号：EP23204590.6
申请日：2023-10-19
发明人： Zhang, Lucas , Gao, Chao , He, Lei
IPC分类号： H01L23/495 , H01L23/00
CPC分类号： H01L23/49513 , H01L23/49548 , H01L23/49524 , H01L23/49562 , H01L24/34 , H01L24/40
摘要： A semiconductor device including a housing, a semiconductor chip disposed within the housing and having first and second metal electrodes, a first lead frame having a first end extending out of the housing and a second end terminating in a die pad, a top surface of the die pad including a cavity having a first quantity of solder disposed therein for electrically connecting the die pad to the first metal electrode, a second lead frame having a first end extending out of the housing and having a second end disposed adjacent the semiconductor chip, and a clip having a first end connected to the second of the lead frame and a second end extending over the semiconductor chip, a bottom surface of the second end of the clip including a recess having a second quantity of solder disposed therein for electrically connecting the clip to the second metal electrode.
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公开(公告)号：EP4340045A1
公开(公告)日：2024-03-20
申请号：EP23197020.3
申请日：2023-09-12
IPC分类号： H01L29/861 , H01L29/06 , H01L21/329 , H01L27/02
摘要： A transient voltage suppression (TVS) device and method of formation. A TVS device may include a first layer, disposed on a first surface of a substrate, comprising a first P+ layer; a second layer, disposed on a second surface of the substrate, opposite the first surface, comprising a second P+ layer; a third layer, disposed between the first P+ layer and the second P+ layer, comprising an N- layer; and an isolation diffusion region, comprising a P structure, connected to the second P+ layer, and extending along a perimeter of the N- layer.
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公开(公告)号：EP4340022A1
公开(公告)日：2024-03-20
申请号：EP23197018.7
申请日：2023-09-12
发明人： Zhang, Lucas , Gao, Chao , He, Lei
IPC分类号： H01L23/495 , H01L23/31
摘要： A surface mounting apparatus, structure, and associated methods thereof. The surface mounting apparatus includes a housing, a lead frame, at least partially encapsulated by the housing. The lead frame includes a chip mounting surface having a chip mounting pad, and one or more first stress relief features disposed outside of the chip mounting surface. The apparatus further includes another lead frame, at least partially encapsulated by the housing. The other lead frame includes one or more second stress relief features
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公开(公告)号：EP3832720A1
公开(公告)日：2021-06-09
申请号：EP20211999.6
申请日：2020-12-04
发明人： ZENG, Jianfei , CAI, Yingda
IPC分类号： H01L27/02 , H01L29/861 , H02H9/04
摘要： In one embodiment, an asymmetric TVS device may include a semiconductor substrate, comprising an inner region, the inner region having a first polarity, and a first surface region, disposed on a first surface of the semiconductor substrate, the first surface region comprising a second polarity, opposite the first polarity. The asymmetric TVS device may also include a second surface region, comprising the second polarity, and disposed on a second surface of the semiconductor substrate, opposite the first surface, wherein the first surface region comprises a first dopant concentration, and wherein the second surface region comprises a second dopant concentration, greater than the first dopant concentration.
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公开(公告)号：EP4358151A2
公开(公告)日：2024-04-24
申请号：EP23203781.2
申请日：2023-10-16
IPC分类号： H01L29/06 , H01L27/02 , H01L29/861 , H01L29/66
CPC分类号： H01L29/861 , H01L29/8613 , H01L29/0615 , H01L29/0657 , H01L27/0248 , H01L29/66136 , H01L29/0661
摘要： A unidirectional transient voltage suppression (TVS) device. The TVS device may include a first layer, comprising an N+ material, formed on a first part of a first main surface of a substrate and a second layer formed from an N- material. The second layer may extend from a second part of the first main surface, surrounding the first layer, and may extend subjacent to the first layer. The TVS device may include a third layer, comprising a P+ material, wherein the second layer is disposed between the first layer and the third layer. The TVS device may also include an isolation region, extending from the first main surface, and being disposed around the second layer.
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公开(公告)号：EP4258349A1
公开(公告)日：2023-10-11
申请号：EP23167218.9
申请日：2023-04-07
发明人： ZHANG, Lucas , ZHOU, Jifeng , CAI, Charlie
IPC分类号： H01L23/495
摘要： A discrete semiconductor package includes a semiconductor device, a left lead, and a right lead. The semiconductor device has a first side and a second side, the second side being opposite the first side. The left lead has a left terminal and a platform to support the semiconductor device on the first side. The right lead has a right terminal and a clip coin to support the semiconductor device on the second side.
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公开(公告)号：EP4258348A1
公开(公告)日：2023-10-11
申请号：EP23167217.1
申请日：2023-04-07
发明人： ZHANG, Lucas , CAI, Charlie , ZHOU, Jifeng
IPC分类号： H01L23/495
摘要： A discrete power semiconductor package includes a semiconductor chip, a heatsink, a first lead, a second lead, and a clip. The heatsink is adjacent the semiconductor chip and draws heat away from the semiconductor chip. The clip binds the semiconductor chip to the heatsink and includes a chip linker, a first terminal, and a second terminal. The chip linker is atop the semiconductor chip. The first terminal connects to the first lead and the second terminal connects to the second lead.
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