公开(公告)号：EP4481576A1

公开(公告)日：2024-12-25

申请号：EP24174916.7

申请日：2024-05-08

Applicant: Winbond Electronics Corp.

Inventor： ADMON, Itay ,  TASHER, Nir

IPC: G06F13/16 ,  G11C7/10 ,  G06F13/42 ,  G06F21/57

Abstract: An IC includes a primary memory die and a secondary memory die. The primary memory die is coupled to a bus providing a primary Chip Select (CS) signal via a primary CS line that connects to the primary memory die. The secondary memory die is coupled to the bus, excluding the primary CS line, and to a secondary CS line carrying a secondary CS signal provided by the primary memory die. The primary memory die is configured to receive a command over the bus, while the primary CS signal is active, in response to identifying that the command is destined to the primary memory die, to execute the command within the primary memory die, and in response to identifying that the command is destined to the secondary memory die, to cause the secondary memory die to execute the command by transferring the primary CS signal on the secondary CS line.

公开(公告)号：EP4257994A1

公开(公告)日：2023-10-11

申请号：EP23161187.2

申请日：2023-03-10

Applicant: Winbond Electronics Corp.

Inventor： KLEIN, Tal ,  ABOUTBOUL, Ronny ,  GLASBERG, Erez ,  AVIGDOR, Yoram

IPC: G01R31/3183 ,  G01R31/319

Abstract: An apparatus for generating Automatic Test Equipment (ATE) testing patterns to test an electronic device-under-test (DUT) that includes electrical circuitry, at least one input port and at least one output port. The apparatus includes a memory and a processor. The memory is configured to store (i) a hardware verification language (HVL) model of the IC, including a model input that models the at least one DUT input port and a model output that models the at least one OUT output port, the HVL model configured to determine, obliviously to the electrical circuitry, a logic state of the model output responsively to a logic state of the model input, and (ii) a simulation program, configured to simulate the HVL model of the DUT. The processor is configured to generate an ATE testing pattern for the DUT by running the simulation program.

公开(公告)号：EP4148735A1

公开(公告)日：2023-03-15

申请号：EP22174096.2

申请日：2022-05-18

Applicant: Winbond Electronics Corp.

Inventor： TANG, Chih-Tung ,  LIN, Chih-Feng

IPC: G11C5/04 ,  G11C5/06 ,  G11C11/4093

Abstract: System on chips, memory circuits, and method for data access, the memory circuits including a memory cell array and an input/output (I/O) connection interface coupled to the memory cell array are provided, wherein the I/O connection interface is configured for coupling to an external signal line to directly receive a transistor-level operation signal from an external memory controller for accessing data in the memory cell array.

公开(公告)号：EP3699913A1

公开(公告)日：2020-08-26

申请号：EP19194512.0

申请日：2019-08-30

Applicant: Winbond Electronics Corp.

Inventor： ADMON, Itay ,  TASHER, Nir ,  LUKO, Mark

IPC: G11C16/20 ,  G11C7/20 ,  G11C7/10 ,  G11C5/14

Abstract: A memory device (108) includes a non-volatile memory (112) and circuitry. The circuitry is configured to initialize and prepare the non-volatile memory (112) for executing memory-access operations for a processor (102), and to ascertain that no memory-access operations are received from the processor (102) before the non-volatile memory (112) is ready, by preventing the processor (102) from bootstrapping during at least part of initialization and preparation of the non-volatile memory (112).

公开(公告)号：EP3236470B1

公开(公告)日：2020-08-05

申请号：EP16197518.0

申请日：2016-11-07

Applicant: Winbond Electronics Corp.

Inventor： Huang, Koying

IPC: G11C7/22 ,  G06F11/10 ,  G11C16/28 ,  G11C16/32

公开(公告)号：EP3226120B1

公开(公告)日：2019-07-17

申请号：EP17163465.2

申请日：2017-03-29

Applicant: Winbond Electronics Corp.

Inventor： KALUZHNY, Uri

IPC: G06F7/523 ,  G06F7/72

公开(公告)号：EP3163642B1

公开(公告)日：2018-08-22

申请号：EP16162207.1

申请日：2016-03-24

Applicant: Winbond Electronics Corp.

Inventor： HSU, Po-Yen ,  SHEN, Ting-Ying ,  HO, Chia-Hua ,  FU, Chih-Cheng ,  CHEN, Frederick

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683

Abstract: Provided are a resistive memory and a method of fabricating the resistive memory. The resistive memory includes a first electrode, a second electrode, a variable resistance layer, an oxygen exchange layer, and a protection layer. The first electrode and the second electrode are arranged opposite to each other. The variable resistance layer is arranged between the first electrode and the second electrode. The oxygen exchange layer is arranged between the variable resistance layer and the second electrode. The protection layer is arranged at least on sidewalls of the oxygen exchange layer.

公开(公告)号：EP3093788B1

公开(公告)日：2018-06-06

申请号：EP15171304.7

申请日：2015-06-10

Applicant: Winbond Electronics Corp.

Inventor： Teper, Valery

IPC: G01R27/26 ,  H04L9/10 ,  G06F21/75 ,  G06F21/85 ,  H01L23/00

CPC classification number: G01R27/2605 ,  G06F21/75 ,  G06F21/755 ,  G06F21/85 ,  G09C1/00 ,  H01L23/576 ,  H04L9/003 ,  H04L9/10 ,  H04L2209/12 ,  H04L2209/122

Abstract: An electronic circuit with protection against eavesdropping, including a first circuit element embedded in the electronic circuit, a second circuit element embedded in the electronic circuit, one or more connection lines between the first circuit element and the second circuit element, a first monitoring unit in the first circuit element for measuring capacitance of at least one of the connection lines between the first circuit element and the second circuit element, wherein the first monitoring unit is configured to identify changes in capacitance of the connection lines and to initiate actions to prevent eavesdropping in response to identifying changes.

公开(公告)号：EP2945092B1

公开(公告)日：2018-05-16

申请号：EP14168529.7

申请日：2014-05-15

Applicant: Winbond Electronics Corp.

Inventor： Tasher, Nir ,  Kaluzhny, Uri ,  Weiser, Tsachi ,  Teper, Valery

IPC: G11C29/12 ,  G11C16/22 ,  G11C7/24 ,  G06F12/14 ,  G06F21/79 ,  G11C29/44

CPC classification number: G11C29/1201 ,  G06F21/79 ,  G11C7/24 ,  G11C16/22 ,  G11C2029/4402

Abstract: A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.

公开(公告)号：EP2930760B1

公开(公告)日：2018-02-07

申请号：EP14182654.5

申请日：2014-08-28

Applicant: Winbond Electronics Corp.

Inventor： Lin, Meng-Heng ,  Wu, Bo-Lun

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/1641 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/15 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: A method includes forming a resistance-switching layer (104) and a second electrode (106) over a first electrode (102). The method includes applying a forming voltage to the resistance-switching layer such that the resistance of the resistance-switching layer is decreased. The method includes applying an initial reset voltage to the first electrode or the second electrode such that the resistance of the resistance-switching layer is increased. The method includes applying a first set voltage to the first electrode or the second electrode such that the resistance of the resistance-switching layer is decreased. The method includes applying a second reset voltage to first electrode or the second electrode such that the resistance of the resistance-switching layer is increased. The method includes applying a second set voltage to first electrode or the second electrode such that the resistance of the resistance-switching layer is decreased. The second set voltage is lower than the first set voltage.