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    LOW-TEMPERATURE POST-DOPANT ACTIVATION PROCESS
    2.
    发明公开
    LOW-TEMPERATURE POST-DOPANT ACTIVATION PROCESS 审中-公开
    低温工艺用于掺杂材料的激活

    公开(公告)号：EP1444725A1

    公开(公告)日：2004-08-11

    申请号：EP02780440.0

    申请日：2002-10-11

    申请人： ADVANCED MICRO DEVICES INC.

    发明人： YU, Bin ,  OGLE, Robert, B. ,  PATON, Eric, N. ,  TABERY, Cyrus, E. ,  XIANG, Qi

    IPC分类号： H01L21/268 ,  H01L21/336

    CPC分类号： H01L29/665 ,  H01L21/268

    摘要： A method of manufacturing a MOSFET semiconductor device comprises forming a gate electrode (24) over a substrate (10) and a gate oxide (16) between the gate electrode (24) and the substrate (10); forming source/drain extensions (30, 32) in the substrate (10); forming first and second sidewall spacers (36, 38); implanting dopants (44) within the substrate (10) to form source/drain regions (40, 42) in the substrate (10) adjacent to the sidewalls spacers (36, 38); laser thermal annealing to activate the source/drain regions (40, 42); depositing a layer of nickel (46) over the source/drain regions (40, 42); and annealing to form a nickel silicide layer (46) disposed on the source/drain regions (40, 42). The source/drain extensions (30, 32) and sidewall spacers (36, 38) are adjacent to the gate electrode (24). The source/drain extensions (30, 32) can have a depth of about 5 to 30 nanometers, and the source/drain regions (40, 42) can have a depth of about 40 to 100 nanometers. The annealing is at temperatures from about 350 to 500 °C.

    TRI-GATE AND GATE AROUND MOSFET DEVICES AND METHODS FOR MAKING SAME
    3.
    发明公开
    TRI-GATE AND GATE AROUND MOSFET DEVICES AND METHODS FOR MAKING SAME 有权
    三栅和门全能MOSFET器件及相关方法

    公开(公告)号：EP1593150A1

    公开(公告)日：2005-11-09

    申请号：EP04702508.5

    申请日：2004-01-15

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： AN, Judy, Xilin ,  WANG, Haihong ,  YU, Bin

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/423

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

    摘要： A triple gate metal-oxide semiconductor field-effect transistor (MOSFET) (200) includes a fin structure (310), a first gate (410) formed adjacent a first side of the fin structure (310), a second gate (420) formed adjacent a second side of the fin structure (310) opposite the first side, and a top gate (610) formed on top of the fin structure (310). A gate around MOSFET (800) includes multiple fins (1110), a first sidewall gate structure (1010) formed adjacent one of the fins (l 110), a second sidewall gate structure (1020) formed adjacent another one of the fins (1110), a top gate structure (1230) formed on one or more of the fins (1110), and a bottom gate structure (1240) formed under one or more of the fins (1110).

    A NOVEL CAPACITIVELY COUPLED DTMOS ON SOI
    6.
    发明公开
    A NOVEL CAPACITIVELY COUPLED DTMOS ON SOI 审中-公开
    一种新颖的kapazitif耦合DTMOS在SOI衬底上

    公开(公告)号：EP1307922A2

    公开(公告)日：2003-05-07

    申请号：EP01931008.5

    申请日：2001-05-01

    申请人： ADVANCED MICRO DEVICES INC.

    发明人： KRISHNAN, Srinath ,  HOLST, John, C. ,  YU, Bin

    IPC分类号： H01L29/10 ,  H01L29/786

    CPC分类号： H01L29/78621 ,  H01L29/7841 ,  H01L29/78612

    摘要： A transistor structure (50) is provided comprising a source region (82, 86) having a N+ drain region (80) and a N' lightly doped drain region (80) and a N' lightly doped drain region (84). AP++ heavily doped (110) is provided. The P++ region (110) resides alongside at least a portion of at least one of the N- lightly doped source region (86) and N- lightly doped drain region (84). AP+ body region (120, 158) resides below a gate (90, 156) of the device (50) and between the source (82, 86) and drain (80, 84) regions. The P++ heavily doped region (110) provides a capacitive coupling between a body region (120, 158) and the gate (90, 156) of the device (50) and form a capacitive voltage divider with the junction capacitance of the device (50).

    TRI-GATE AND GATE AROUND MOSFET DEVICES AND METHODS FOR MAKING SAME
    8.
    发明授权
    TRI-GATE AND GATE AROUND MOSFET DEVICES AND METHODS FOR MAKING SAME 有权
    三栅和门全能MOSFET器件及相关方法

    公开(公告)号：EP1593150B1

    公开(公告)日：2007-08-08

    申请号：EP04702508.5

    申请日：2004-01-15

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： AN, Judy, Xilin ,  WANG, Haihong ,  YU, Bin

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/423

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

    摘要： A triple gate metal-oxide semiconductor field-effect transistor (MOSFET) (200) includes a fin structure (310), a first gate (410) formed adjacent a first side of the fin structure (310), a second gate (420) formed adjacent a second side of the fin structure (310) opposite the first side, and a top gate (610) formed on top of the fin structure (310). A gate around MOSFET (800) includes multiple fins (1110), a first sidewall gate structure (1010) formed adjacent one of the fins (l 110), a second sidewall gate structure (1020) formed adjacent another one of the fins (1110), a top gate structure (1230) formed on one or more of the fins (1110), and a bottom gate structure (1240) formed under one or more of the fins (1110).