公开(公告)号：EP1550164A1

公开(公告)日：2005-07-06

申请号：EP03752303.2

申请日：2003-09-12

申请人： ADVANCED MICRO DEVICES INC.

发明人： PATON, Eric, N. ,  XIANG, Qi ,  BESSER, Paul, R. ,  LIN, Ming-Ren ,  NGO, Minh, Van ,  WANG, Haihong

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/28 ,  H01L29/49

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66795 ,  H01L2029/7858

摘要： A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide (62, 64) that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.

公开(公告)号：EP1186017A2

公开(公告)日：2002-03-13

申请号：EP00912061.9

申请日：2000-02-29

申请人： ADVANCED MICRO DEVICES INC.

发明人： XIANG, Qi ,  BUYNOSKI, Matthew, S. ,  LIN, Ming-Ren

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/7833

摘要： A method of fabricating a transistor having shallow source and drain extensions utilizes a self-aligned contact. The drain extensions are provided through an opening between a contact area and the gate structure. A high-k gate dielectric material can be utilized. P-MOS and N-MOS transistors can be created according to the disclosed method.

公开(公告)号：EP1815531A1

公开(公告)日：2007-08-08

申请号：EP05812228.4

申请日：2005-10-12

申请人： ADVANCED MICRO DEVICES, INC.

发明人： XIANG, Qi ,  SUBBA, Niraj ,  MASZARA, Witold, P. ,  KRIVOKAPIC, Zoran ,  LIN, Ming-Ren

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

摘要： A semiconductor substrate (102) is provided having an insulator (104) thereon with a semiconductor layer (106) on the insulator (104). A deep trench isolation (108) is formed, introducing strain to the semiconductor layer (106). A gate dielectric (202) and a gate (204) are formed on the semiconductor layer (106). A spacer (304) is formed around the gate (204), and the semiconductor layer (106) and the insulator (104) are removed outside the spacer (304). Recessed source/drain (402) are formed outside the spacer (304).

公开(公告)号：EP1723668A1

公开(公告)日：2006-11-22

申请号：EP04815218.5

申请日：2004-12-21

申请人： ADVANCED MICRO DEVICES, INC.

发明人： XIANG, Qi ,  PAN, James, N. ,  GOO, Jung-Suk

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842

摘要： An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer (140) above an insulating layer (130), providing a trench (142) in the compound semiconductor layer (140), and providing a strained semiconductor layer (144) above the compound semiconductor layer (140) and within the trench (142). The method can also include removing the strained semiconductor layer (144) from above the compound semiconductor layer (140), thereby leaving the strained semiconductor layer (144) within the trench (142) and removing the compound semiconductor layer (140) to leave the strained semiconductor layer (144) and form the fin-shaped channel region (152).

公开(公告)号：EP1552554A2

公开(公告)日：2005-07-13

申请号：EP03799836.6

申请日：2003-10-14

申请人： ADVANCED MICRO DEVICES INC.

发明人： WRISTERS, Derick, J. ,  XIANG, Qi ,  BULLER, James, F.

IPC分类号： H01L21/762

CPC分类号： H01L29/78696 ,  H01L29/1054 ,  H01L29/66772 ,  H01L29/7846 ,  H01L29/78603

摘要： A semiconductor device is provided with the high-speed capabilities of silicon on insulator (SOI) and strained silicon technologies, without requiring the formation of a silicon germanium layer. A layer of compressive material (22) is formed on a SOI semiconductor substrate (20) to induce strain in the overlying silicon layer (21). The compressive materials include silicon oxynitride, phosphorus, silicon nitride, and boron/phosphorus doped silica glass.

公开(公告)号：EP1547156B1

公开(公告)日：2010-12-15

申请号：EP03799284.9

申请日：2003-09-12

申请人： ADVANCED MICRO DEVICES, INC.

发明人： LIN, Ming-Ren ,  GOO, Jung-Suk ,  WANG, Haihong ,  XIANG, Qi

IPC分类号： H01L29/786 ,  H01L29/423 ,  H01L21/336 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

摘要： A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body (46) is patterned from a layer of silicon germanium (SiGe) (42) that overlies a dielectric layer (40). An epitaxial layer of silicon (34) is then formed on the silicon germanium FinFET body (46). A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.

公开(公告)号：EP1723668B1

公开(公告)日：2007-05-30

申请号：EP04815218.5

申请日：2004-12-21

申请人： ADVANCED MICRO DEVICES, INC.

发明人： XIANG, Qi ,  PAN, James, N. ,  GOO, Jung-Suk

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842

摘要： An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer (140) above an insulating layer (130), providing a trench (142) in the compound semiconductor layer (140), and providing a strained semiconductor layer (144) above the compound semiconductor layer (140) and within the trench (142). The method can also include removing the strained semiconductor layer (144) from above the compound semiconductor layer (140), thereby leaving the strained semiconductor layer (144) within the trench (142) and removing the compound semiconductor layer (140) to leave the strained semiconductor layer (144) and form the fin-shaped channel region (152).

公开(公告)号：EP1661177A2

公开(公告)日：2006-05-31

申请号：EP04816840.5

申请日：2004-08-31

申请人： ADVANCED MICRO DEVICES, INC.

发明人： XIANG, Qi ,  ZHONG, Huicai ,  GOO, Jung-Suk ,  HOLBROOK, Allison, Kay ,  JEON, Joong, S. ,  KLUTH, George, Jonathan

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： According to one exemplary embodiment, a method for integrating first (206) and second metal layers (208) on a substrate (202) to form a dual metal NMOS gate (226) and PMOS gate (228) comprises depositing (150) a dielectric layer (204) over an NMOS region (210) and a PMOS region (212) of the substrate (202). The method further comprises depositing (150) the first metal layer (206) over dielectric layer (204). The method further comprises depositing (150) the second metal layer (208) over the first metal layer (206). The method further comprises implanting (152) nitrogen in the NMOS region (210) of substrate (202) and converting (154) a first portion of the first metal layer (206) into a metal oxide layer (220) and converting a second portion of the first metal layer (206) into metal nitride layer (218). The method further comprises forming (156) the NMOS gate (226) and the PMOS gate (228), where the NMOS gate (226) comprises a segment (234) of metal nitride layer (218) and the PMOS gate (228) comprises a segment (242) of the metal oxide layer (220).

公开(公告)号：EP1550164B1

公开(公告)日：2012-04-18

申请号：EP03752303.2

申请日：2003-09-12

申请人： ADVANCED MICRO DEVICES, INC.

发明人： PATON, Eric, N. ,  XIANG, Qi ,  BESSER, Paul, R. ,  LIN, Ming-Ren ,  NGO, Minh, Van ,  WANG, Haihong

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/28 ,  H01L29/49

CPC分类号： H01L29/4933 ,  H01L21/28052 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66795 ,  H01L2029/7858

摘要： A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide (62, 64) that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.

公开(公告)号：EP1661177B1

公开(公告)日：2009-08-26

申请号：EP04816840.5

申请日：2004-08-31

申请人： ADVANCED MICRO DEVICES, INC.

发明人： XIANG, Qi ,  ZHONG, Huicai ,  GOO, Jung-Suk ,  HOLBROOK, Allison, Kay ,  JEON, Joong, S. ,  KLUTH, George, Jonathan

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： According to one exemplary embodiment, a method for integrating first (206) and second metal layers (208) on a substrate (202) to form a dual metal NMOS gate (226) and PMOS gate (228) comprises depositing (150) a dielectric layer (204) over an NMOS region (210) and a PMOS region (212) of the substrate (202). The method further comprises depositing (150) the first metal layer (206) over dielectric layer (204). The method further comprises depositing (150) the second metal layer (208) over the first metal layer (206). The method further comprises implanting (152) nitrogen in the NMOS region (210) of substrate (202) and converting (154) a first portion of the first metal layer (206) into a metal oxide layer (220) and converting a second portion of the first metal layer (206) into metal nitride layer (218). The method further comprises forming (156) the NMOS gate (226) and the PMOS gate (228), where the NMOS gate (226) comprises a segment (234) of metal nitride layer (218) and the PMOS gate (228) comprises a segment (242) of the metal oxide layer (220).