公开(公告)号：EP1459353A2

公开(公告)日：2004-09-22

申请号：EP02784777.1

申请日：2002-12-10

申请人： Applied Materials, Inc.

发明人： DING, Peijun ,  XU, Zheng ,  MOSELY, Roderick, C. ,  RENGARAJAN, Suraj ,  MAITY, Nirmalya ,  CARL, Daniel, A. ,  CHIN, Barry ,  SMITH, Paul, F. ,  ANGELO, Darryl ,  TOLIA, Anish ,  FU, Jianming ,  CHEN, Fusen ,  GOPALRAJA, Praburam ,  TANG, Xianmin ,  FORSTER, John, C.

IPC分类号： H01J37/34 ,  H01J37/32

CPC分类号： H01L21/76844 ,  C23C14/046 ,  C23C14/345 ,  C23C14/3457 ,  C23C14/358 ,  H01J37/321 ,  H01J37/3408 ,  H01J2237/3327 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2221/1089

摘要： A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same chamber. Also, bottom coverage may be thinned or eliminated by ICP resputtering. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering.

公开(公告)号：EP1042806A1

公开(公告)日：2000-10-11

申请号：EP98956499.2

申请日：1998-11-02

申请人： APPLIED MATERIALS, INC.

发明人： DING, Peijun ,  CHIANG, Tony ,  CHIN, Barry

IPC分类号： H01L23/532

CPC分类号： H01L21/76843 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed herein is a barrier layer structure useful in forming copper interconnects and electrical contacts of semiconductor devices. The barrier layer structure comprises a first layer of TaNx which is applied directly over the substrate, followed by a second layer of Ta. The TaNx/Ta barrier layer structure provides both a barrier to the diffusion of a copper layer deposited thereover, and enables the formation of a copper layer having a high {111} crystallographic content so that the electromigration resistance of the copper is increased. The TaNx layer, where x ranges from about 0.1 to about 1.5, is sufficiently amorphous to prevent the diffusion of copper into the underlying substrate, which is typically silicon or a dielectric such as silicon dioxide. The thickness of the TaNx and Ta layers used for an interconnect depend on the feature size and aspect ratio; typically, the TaNx layer thickness ranges from about 50 Å to about 1,000 Å, while the Ta layer thickness ranges from about 20 Å to about 500 Å. For a contact via, the permissible layer thickness on the via walls must be even more carefully controlled based on feature size and aspect ratio; typically, the TaNx layer thickness ranges from about 10 Å to about 300 Å, while the Ta layer thickness ranges from about 5 Å to about 300 Å. The copper layer is deposited at the thickness desired to suit the needs of the device. The copper layer may be deposited using any of the preferred techniques known in the art. Preferably, the entire copper layer, or at least a 'seed' layer of copper, is deposited using physical vapor deposition techniques such as sputtering or evaporation, as opposed to CVD or electroplating. Since the crystal orientation of the copper is sensitive to deposition temperature, and since the copper may tend to dewet/delaminate from the barrier layer if the temperature is too high, it is important that the copper be deposited and/or annealed at a temperature of less than about 500 °C, and preferably at a temperature of less than about 300 °C.

公开(公告)号：EP1115898A1

公开(公告)日：2001-07-18

申请号：EP99949747.2

申请日：1999-09-21

申请人： Applied Materials, Inc.

发明人： CHIANG, Tony ,  DING, Peijun ,  CHIN, Barry

IPC分类号： C23C14/16 ,  C23C14/06 ,  H01L21/768 ,  H01L21/285

CPC分类号： H01L21/76843 ,  C23C14/0641 ,  C23C14/165 ,  C23C14/541 ,  C23C14/5806 ,  H01L21/28556 ,  H01L21/318 ,  H01L21/76864 ,  Y10T428/31678

摘要： We have discovered that, by depositing a tantalum layer upon a substrate at a temperature of at least 325 °C, it is possible to obtain an ultra low resistivity. In addition, it is possible to deposit a TaxNy film having an ultra low resistivity by depositing the TaxNy film upon a substrate at a temperature of at least 275 °C, wherein x is 1 and y ranges from about 0.05 to about 0.18. A combination of elevated substrate temperature and ion bombardment of the film surface during deposition enables the use of lower substrate temperatures while maintaining film properties. In another development, we have discovered that the ultra low resistivity tantalum and TaxNy films produced by the method of the present invention also exhibit particularly low residual stress. Further, these films can be chemical mechanical polished at significantly higher rates (at least 40 % higher rates) than higher resistivity tantalum and TaxNy. This is particularly useful in damascene processes when copper is used as the interconnect metal, since it reduces the possibility of copper dishing during a polishing step.

公开(公告)号：EP1099250A2

公开(公告)日：2001-05-16

申请号：EP99937492.9

申请日：1999-07-26

申请人： APPLIED MATERIALS, INC.

发明人： HASHIM, Imran ,  CHIANG, Tony ,  CHIN, Barry

IPC分类号： H01L21/768

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter-etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.

公开(公告)号：EP1034566A1

公开(公告)日：2000-09-13

申请号：EP98956259.0

申请日：1998-10-26

申请人： Applied Materials, Inc.

发明人： CHIANG, Tony ,  YAO, Gongda ,  DING, Peijun ,  CHEN, Fusen ,  CHIN, Barry ,  KOHARA, Gene ,  XU, Zheng ,  ZHANG, Hong

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first position of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using an ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) of the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.