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    Method and apparatus for orienting substrates
    1.
    发明公开
    Method and apparatus for orienting substrates 审中-公开
    Verfahren und Vorrichtung zur Ausrichtung von Substraten

    公开(公告)号：EP1117128A2

    公开(公告)日：2001-07-18

    申请号：EP01300056.7

    申请日：2001-01-04

    申请人： Applied Materials, Inc.

    发明人： Perlov, Ilya ,  Gantvarg, Eugene ,  Tertitski, Leonid

    IPC分类号： H01L21/00

    CPC分类号： H01L21/681 ,  Y10S414/136 ,  Y10S414/138

    摘要： A multiple substrate orienter (100) is provided that includes a rotatable substrate handler (102) having a plurality of substrate support portions (104a-e), each adapted to support a substrate. The multiple substrate orienter also includes a plurality of stacked substrate supports, each adapted to support a substrate. A plurality of substrate orientation marking (SOM) detectors (108a-e) are provided, and each SOM detector is coupled to a different one of the substrate supports and is adapted to identify a presence of an SOM of a substrate positioned close enough to the SOM detector to allow SOM detection by the SOM detector. The multiple substrate orienter further includes a plurality of lift and lower mechanisms (106a-e), each lift and lower mechanism coupled to a different one of the substrate supports and adapted to individually lift and lower the substrate support to which the lift and lower mechanism is coupled. Alternatively, each lift and lower mechanism may be coupled to a different one of the substrate support portions of the rotatable substrate handler and adapted to individually lift and lower the substrate support portion to which the lift and lower mechanism is coupled. Preferably the multiple substrate orienter includes a controller (109) having program code adapted to simultaneously rough orient a plurality of substrates loaded onto the substrate support portions of the substrate handler, and to individually fine orient each rough oriented substrate. In further aspects of the invention, a substrate orienter capable or orienting one or more substrates is provided, as are methods for orienting substrates as described above.

    摘要翻译： 提供了多个基板取向器（100），其包括具有多个基板支撑部分（104a-e）的可旋转基板处理器（102），每个基板支撑部分适于支撑基板。 多个基板取向器还包括多个堆叠的基板支撑件，每个基板支撑件适于支撑基板。 提供了多个基板取向标记（SOM）检测器（108a-e），并且每个SOM检测器耦合到不同的一个基板支撑件，并且适于识别基板的SOM的位置， SOM检测器允许SOM检测器进行SOM检测。 多个基板定向器还包括多个提升和下部机构（106a-e），每个提升和下部机构联接到不同的一个基板支撑件并且适于独立地提升和降低基板支撑件，升降机构和下部机构 被耦合。 或者，每个提升和下部机构可以联接到可旋转衬底处理器的不同的一个衬底支撑部分，并且适于单独升高和降低升降机构和下部机构所联接的衬底支撑部分。 优选地，多个基板取向器包括具有程序代码的控制器（109），该程序代码适用于同时粗略地定向加载到基板处理器的基板支撑部分上的多个基板，并且单独精细地定向每个粗略取向的基板。 在本发明的另一方面，提供了能够或定向一个或多个基板的基板取向器，如上所述的用于定向基板的方法。

    Thermal reaction chamber for semiconductor wafer processing operations
    5.
    发明公开
    Thermal reaction chamber for semiconductor wafer processing operations 失效
    Thermische ReaktionskammerfürOperationen zur Bearbeitung von Halbleiter-Wafer。

    公开(公告)号：EP0613173A1

    公开(公告)日：1994-08-31

    申请号：EP94103000.9

    申请日：1994-02-28

    申请人： APPLIED MATERIALS, INC.

    发明人： Perlov, Ilya

    IPC分类号： H01L21/00

    CPC分类号： H01L21/68742 ,  H01L21/67115 ,  H01L21/68792

    摘要： A thermal reaction chamber (30) for semiconductor wafer processing operations comprising:

    (i) a susceptor (36) for supporting a semiconductor wafer (38) within the chamber (32) and having a plurality of apertures (70) formed vertically therethrough;
    (ii) displacer means (35) for displacing the susceptor (36) vertically between at least a first and a second position;
    (iii) a plurality of wafer support elements (66), each of which is suspended to be vertically moveable within said apertures (70) and each of which extends beyond the underside of the susceptor (36); and
    (iv) means (64) for restricting the downward movement of the wafer support elements (66). As the susceptor is displaced from its first position through an intermediate position before the second position, the means (64) for restricting operate to stop the continued downward movement of the wafer support elements (66) thereby causing the elements to move vertically upwards with respect to the downwardly moving susceptor (36) and separate the wafer (38) from the susceptor (36).

    摘要翻译： 一种用于半导体晶片处理操作的热反应室（30），包括：（i）用于在腔室（32）内支撑半导体晶片（38）并具有垂直穿过其中形成的多个孔（70）的基座（36） （ii）用于在至少第一和第二位置之间垂直移动所述基座（36）的置换器装置（35） （iii）多个晶片支撑元件（66），每个晶片支撑元件悬挂在所述孔（70）内可垂直移动，并且每个延伸超出基座（36）的下侧; 和（iv）用于限制晶片支撑元件（66）向下移动的装置（64）。 当基座从第一位置移动到第二位置之前的中间位置时，用于限制的装置（64）操作以停止晶片支撑元件（66）的持续向下移动，从而使元件相对于 到所述向下移动的基座（36）并将所述晶片（38）与所述基座（36）分离。

    TEOS based plasma enhanced chemical vapor deposition process for deposition of silicon dioxide films.
    6.
    发明公开
    TEOS based plasma enhanced chemical vapor deposition process for deposition of silicon dioxide films. 失效
    热CVD / PECVD反应器和用于二氧化硅和本地多步平面化方法的热化学气相沉积的用途

    公开(公告)号：EP0272140A3

    公开(公告)日：1990-11-14

    申请号：EP87311193.4

    申请日：1987-12-18

    申请人： APPLIED MATERIALS, INC.

    发明人： Wang, David Nin-Kou ,  White, John M. ,  Law, Kam S. ,  Leung, Cissy ,  Umotoy, Salvador P. ,  Collins, Kenneth S. ,  Adamik, John A. ,  Perlov, Ilya ,  Maydan, Dan

    IPC分类号： C23C16/54 ,  C23C16/50 ,  C23C16/40 ,  H01L21/316

    CPC分类号： C23C16/45565 ,  C23C16/402 ,  C23C16/455 ,  C23C16/45521 ,  C23C16/5096 ,  C23C16/54 ,  H01J37/32082 ,  H01J37/3244 ,  H01L21/31604

    摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor (10) is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor (16) and wafer fingers (20) which collectively remove the wafer (15) from a robot transfer blade (24) and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold (26) then return the wafer to the blade. A combined RF/gas feed-through device (36) protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold (26) is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust fases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressure including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone on in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

    Chemical vapor deposition chamber
    8.
    发明公开
    Chemical vapor deposition chamber 失效
    化学气相沉积室

    公开(公告)号：EP0619381A1

    公开(公告)日：1994-10-12

    申请号：EP94105139.3

    申请日：1994-03-31

    申请人： APPLIED MATERIALS, INC.

    发明人： Lei, Lawrence Chung-Lai ,  Perlov, Ilya ,  Littau, Karl Anthony ,  Morrison, Alan Ferris ,  Chang, Mei ,  Sinha, Ashok K.

    IPC分类号： C23C16/00 ,  C23C16/44 ,  C23C16/46 ,  H01L21/00

    CPC分类号： C23C16/45519 ,  C23C16/4412 ,  C23C16/45521 ,  C23C16/458 ,  C23C16/4583 ,  C23C16/4585 ,  C23C16/46 ,  H01L21/67103 ,  H01L21/68 ,  H01L21/68721 ,  H01L21/68728 ,  H01L21/68735 ,  H01L21/6875 ,  H01L21/68785 ,  H01L21/68792 ,  Y10S438/935

    摘要： Vacuum CVD chambers are disclosed which provide a more uniformly deposited thin film on a substrate (14). The chamber susceptor mount (210) for the substrate (14) is heated resistively with a single coil firmly contacting the metal of the susceptor on all sides, providing uniform temperatures across the susceptor mount (210) for a substrate (14). A purge gas line (222) is connected to openings in the susceptor outside of the periphery of the substrate (14) to prevent edge and backside contamination of the substrate (14). A vacuum feed line mounts the substrate to the susceptor (210) during processing. A refractory purge guide (226), or a plurality of placement pins, maintain a fixed gap passage for the purge gases to pass alongside the edge of the wafer (14) and into the processing area of the chamber. An exhaust pumping plate improves the uniformity of exhaustion of spent gases from the chamber.

    摘要翻译： 公开了在衬底（14）上提供更均匀沉积的薄膜的真空CVD室。 利用单个线圈在所有侧面上牢固地接触基座的金属来电阻加热用于基板（14）的腔室基座支架（210），从而为基板（14）提供跨基座支架（210）的均匀温度。 净化气体管线（222）连接到衬底（14）周边外部的衬托器中的开口，以防止衬底（14）的边缘和背面污染。 在处理期间，真空馈送线将衬底安装到基座（210）。 耐火净化引导件（226）或多个定位销保持用于净化气体沿着晶片（14）的边缘并且进入腔室的处理区域的固定间隙通道。 排气泵板改善了从腔室中排出的废气的均匀性。

    TEOS based plasma enhanced chemical vapor deposition process for deposition of silicon dioxide films.
    9.
    发明公开
    TEOS based plasma enhanced chemical vapor deposition process for deposition of silicon dioxide films. 失效
    等离子体辅助为二氧化硅的制备TEOS基础的CVD法。

    公开(公告)号：EP0272140A2

    公开(公告)日：1988-06-22

    申请号：EP87311193.4

    申请日：1987-12-18

    申请人： APPLIED MATERIALS, INC.

    发明人： Wang, David Nin-Kou ,  White, John M. ,  Law, Kam S. ,  Leung, Cissy ,  Umotoy, Salvador P. ,  Collins, Kenneth S. ,  Adamik, John A. ,  Perlov, Ilya ,  Maydan, Dan

    IPC分类号： C23C16/54 ,  C23C16/50 ,  C23C16/40 ,  H01L21/316

    CPC分类号： C23C16/45565 ,  C23C16/402 ,  C23C16/455 ,  C23C16/45521 ,  C23C16/5096 ,  C23C16/54 ,  H01J37/32082 ,  H01J37/3244 ,  H01L21/31604

    摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor (10) is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor (16) and wafer fingers (20) which collectively remove the wafer (15) from a robot transfer blade (24) and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold (26) then return the wafer to the blade. A combined RF/gas feed-through device (36) protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold (26) is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust fases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressure including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone on in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

    摘要翻译： 的高压，高吞吐量，单晶片，半导体处理反应器（10）是圆盘游离缺失所有其能够热CVD，等离子体增强CVD，等离子体辅助回蚀，等离子体自洁，和沉积地形修改的通过溅射，或者单独地或者 如原位多步骤处理的一部分。 该反应器包括叉指式基座（16）和晶片的手指（20），其共同地除去来自机器人的转印刮板（24）的晶片（15）和与所述晶片和之间可变，对照，靠近的平行间隔的晶片位置的配合阵列 室气体入口歧管（26），然后将晶片返回到刀片。 组合的RF /气体馈通装置（36）可防止工艺气体泄漏和施加RF能量至气体入口歧管没有内部故障或气体的沉积。 气体入口歧管（26）被用于angepasst在晶片提供均匀的气流。 温度控制的内部和外部的歧管表面抑制外部表面上的冷凝，过早反应和分解和沉积。 因此，反应器集成了一个均匀的径向泵送气体系统，其跨所述晶片和ausrichtet净化气流向下和向上朝向晶片的周缘使扫排气fases从晶片径向远离，以防止沉积在晶片外，并保持均匀的反应气体流 在室清洗。 将反应器在宽范围的压力包括非常高的压力提供均匀的处理。 用于形成二氧化硅的高度保形层的低温CVD方法因此游离缺失盘。 该方法使用非常高的腔室压力和低温，和TEOS和臭氧的反应物。 低温CVD二氧化硅沉积步骤是用于平坦化下层台阶的介电层是特别有用的，无论是单独一个结合随后的各向同性蚀刻。 用于形成平坦化二氧化硅层的用途在低温和高压其次（2）保形二氧化硅层的沉积，从而在高压和（1）高速率的二氧化硅沉积的优选的原位多步骤的过程 低温，通过（3）的高率各向同性蚀刻其次，优选在低温和高压在用于两个氧化物沉积步骤相同的反应器中。 的步骤的各种组合是游离缺失盘针对不同的应用，如一个优选的反应器的自清洁步骤。

    Thermal reaction chamber for semiconductor wafer processing operations
    10.
    发明公开
    Thermal reaction chamber for semiconductor wafer processing operations 失效
    用于处理半导体晶片的热反应室

    公开(公告)号：EP1067588A3

    公开(公告)日：2006-05-31

    申请号：EP00121439.4

    申请日：1994-02-28

    申请人： APPLIED MATERIALS, INC.

    发明人： Perlov, Ilya

    IPC分类号： H01L21/00

    CPC分类号： H01L21/68742 ,  H01L21/67115 ,  H01L21/68792

    摘要： A thermal reaction chamber (30) for semiconductor wafer processing operations comprising:

    (i) a susceptor (36) for supporting a semiconductor wafer (38) within the chamber (32) and having a plurality of apertures (70) formed vertically therethrough;
    (ii) displacer means (35) for displacing the susceptor (36) vertically between at least a first and a second position;
    (iii) a plurality of wafer support elements (66), each of which is suspended to be vertically moveable within said apertures (70) and each of which extends beyond the underside of the susceptor (36); and
    (iv) means (64) for restricting the downward movement of the wafer support elements (66). As the susceptor is displaced from its first position through an intermediate position before the second position, the means (64) for restricting operate to stop the continued downward movement of the wafer support elements (66) thereby causing the elements to move vertically upwards with respect to the downwardly moving susceptor (36) and separate the wafer (38) from the susceptor (36).
    (v) the plurality of wafer support elements (66) comprising heads to shut off all said apertures through the susceptor.