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1.发明公开High-speed dielectrically isolated devices utilizing buried silicide regions and fabrication thereof 失效高速电介质隔离器件利用铜硅化物区域及其制造方法
公开(公告)号：EP0335557A3
公开(公告)日：1989-11-23
申请号：EP89302763.1
申请日：1989-03-21
申请人： AT&T Corp.
IPC分类号： H01L21/74 , H01L21/76 , H01L29/72 , H01L29/78 , H01L21/225
CPC分类号： H01L21/76297 , H01L21/2257 , H01L21/74 , Y10S148/019 , Y10S148/123 , Y10S148/147
摘要： A dielectrically-isolated structure and method of fabricating the same is disclosed wherein the structure includes a layer of silicide (20) which is selectively doped, preferably using an ion implantation process. The doped silicide is then used as the diffusion source for the subsequent formation (through a heat treatment) of various active portions (collector, emitter, drain, source, for example) of a variety of high-voltage, high-speed active devices. The non-doped silicide is advantageously utilized as a low-resistance contact between the buried diffusion region and the surface electrode.
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2.发明授权High-speed dielectrically isolated devices utilizing buried silicide regions and fabrication thereof 失效在高速，埋硅化物区域，其制备方法介质隔离装置。
公开(公告)号：EP0335557B1
公开(公告)日：1995-09-27
申请号：EP89302763.1
申请日：1989-03-21
申请人： AT&T Corp.
IPC分类号： H01L21/74 , H01L21/76 , H01L29/72 , H01L29/78 , H01L21/225
CPC分类号： H01L21/76297 , H01L21/2257 , H01L21/74 , Y10S148/019 , Y10S148/123 , Y10S148/147
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3.发明公开High-speed dielectrically isolated devices utilizing buried silicide regions and fabrication thereof 失效在高速，埋硅化物区域，其制备方法介质隔离装置。
公开(公告)号：EP0335557A2
公开(公告)日：1989-10-04
申请号：EP89302763.1
申请日：1989-03-21
申请人： AT&T Corp.
IPC分类号： H01L21/74 , H01L21/76 , H01L29/72 , H01L29/78 , H01L21/225
CPC分类号： H01L21/76297 , H01L21/2257 , H01L21/74 , Y10S148/019 , Y10S148/123 , Y10S148/147
摘要： A dielectrically-isolated structure and method of fabricating the same is disclosed wherein the structure includes a layer of silicide (20) which is selectively doped, preferably using an ion implantation process. The doped silicide is then used as the diffusion source for the subsequent formation (through a heat treatment) of various active portions (collector, emitter, drain, source, for example) of a variety of high-voltage, high-speed active devices. The non-doped silicide is advantageously utilized as a low-resistance contact between the buried diffusion region and the surface electrode.
摘要翻译： 甲介电隔离结构及其制造方法是游离缺失worin结构盘包括硅化物（20），所有这些被选择性地掺杂，优选使用离子注入处理的层。 然后，将掺杂的硅化物被用作用于各种高压，高速的有源器件的各个活性部分（集电极，发射极，漏极，源极，例如）的后续形成（通过热处理）的扩散源。 非掺杂的硅化物被有利地用作埋置扩散区和表面电极之间的低电阻接触。
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4.发明公开Method of forming semiconductor device structures including dielectrically isolated tubs 失效形成包含电介质隔离TUBS的半导体器件结构的方法
公开(公告)号：EP0311309A3
公开(公告)日：1991-02-06
申请号：EP88309081.3
申请日：1988-09-30
申请人： AT&T Corp.
IPC分类号： H01L21/76
CPC分类号： H01L21/02381 , H01L21/02639 , H01L21/76297 , Y10S148/05
摘要： A method has been developed for altering the resistivity value and/or conductivity type of selected tubs in a dielectrically isolated (DI) wafer. Subsequent to the formation of the conventional tub structure, the wafer is covered with a patterning layer (20) which is etched to expose the selected tubs. Material is then removed from these tubs by etching and material (24, 26) having a new resistivity value and/or conductivity type is grown in the empty tub regions.
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5.发明公开
公开(公告)号：EP0561532A3
公开(公告)日：1997-08-20
申请号：EP93301634.7
申请日：1993-03-04
申请人： AT&T Corp.
IPC分类号： H01L21/20 , H01L21/76 , H01L21/306
CPC分类号： H01L21/76251 , H01L21/30625 , Y10S148/012 , Y10S438/977
摘要： A process for planarizing a bonded wafer (5). The wafer has a layer of exposed oxide (4) thereon which acts as a reference for the grinding and polishing of the wafer. The resulting ground and polished wafer has a thinned, substantially planar, working layer (1) for subsequent fabrication of transistors, etc.
摘要翻译： 用于平坦化接合晶片（5）的工艺。 晶片具有一层暴露的氧化物（4），其作为晶片研磨和抛光的基准。 所得到的研磨和抛光的晶片具有薄的，基本平坦的工作层（1），用于随后制造晶体管等。
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6.发明公开Method of manufacturing an integrated circuit including planarizing a wafer 失效一种用于制备含有所述集成电路的晶片的平坦化处理。
公开(公告)号：EP0561532A2
公开(公告)日：1993-09-22
申请号：EP93301634.7
申请日：1993-03-04
申请人： AT&T Corp.
IPC分类号： H01L21/20 , H01L21/76 , H01L21/306
CPC分类号： H01L21/76251 , H01L21/30625 , Y10S148/012 , Y10S438/977
摘要： A process for planarizing a bonded wafer (5). The wafer has a layer of exposed oxide (4) thereon which acts as a reference for the grinding and polishing of the wafer. The resulting ground and polished wafer has a thinned, substantially planar, working layer (1) for subsequent fabrication of transistors, etc.
摘要翻译： 一种用于贴合晶片（5）平坦化处理。 晶片具有暴露的氧化层（4）在其上的作为用于晶片的研磨和抛光的参考。 所得的研磨和抛光的晶片具有薄型化，对于晶体管的后续制造等基本平坦的工作层（1）
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公开(公告)号：EP0329309A3
公开(公告)日：1991-03-13
申请号：EP89301054.6
申请日：1989-02-03
申请人： AT&T Corp.
IPC分类号： H01L21/76
CPC分类号： H01L21/76297
摘要： A method has been developed for providing tub regions with various resistivities in a dielectrically isolated (DI) structure. The starting substrate material is etched to expose the locations designated for a resistivity modification, and epitaxial material of the modified resistivity value is used to fill the exposed tubs. The remainder of the fabrication process follows conventional DI fabrication techniques. The procedure may simply be used to create a DI structure containing both n-type and p-type tub regions. The idea may also be extended, however, to providing separate tubs with, for example, n+ resistivity, n- resistivity, p- resistivity and p+ resistivity, all within the same DI structure.
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公开(公告)号：EP0329309A2
公开(公告)日：1989-08-23
申请号：EP89301054.6
申请日：1989-02-03
申请人： AT&T Corp.
IPC分类号： H01L21/76
CPC分类号： H01L21/76297
摘要： A method has been developed for providing tub regions with various resistivities in a dielectrically isolated (DI) structure. The starting substrate material is etched to expose the locations designated for a resistivity modification, and epitaxial material of the modified resistivity value is used to fill the exposed tubs. The remainder of the fabrication process follows conventional DI fabrication techniques. The procedure may simply be used to create a DI structure containing both n-type and p-type tub regions. The idea may also be extended, however, to providing separate tubs with, for example, n+ resistivity, n- resistivity, p- resistivity and p+ resistivity, all within the same DI structure.
摘要翻译： 已经开发了一种在介电隔离（DI）结构中提供具有各种电阻率的槽区的方法。 蚀刻起始衬底材料以暴露指定为电阻率修饰的位置，并且使用改进的电阻率值的外延材料来填充暴露的浴缸。 制造工艺的其余部分遵循常规的DI制造技术。 该过程可以简单地用于产生包含n型和p型桶区域的DI结构。 然而，该想法也可以扩展到提供具有例如n +电阻率，n-电阻率，p-电阻率和p +电阻率的单独的桶，全部在相同的DI结构内。
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9.发明公开Method of forming semiconductor device structures including dielectrically isolated tubs 失效Verfahren zur Herstellung von Halbleiteranordnungen mit dielektrisch isolierten Zonen。
公开(公告)号：EP0311309A2
公开(公告)日：1989-04-12
申请号：EP88309081.3
申请日：1988-09-30
申请人： AT&T Corp.
IPC分类号： H01L21/76
CPC分类号： H01L21/02381 , H01L21/02639 , H01L21/76297 , Y10S148/05
摘要： A method has been developed for altering the resistivity value and/or conductivity type of selected tubs in a dielectrically isolated (DI) wafer. Subsequent to the formation of the conventional tub structure, the wafer is covered with a patterning layer (20) which is etched to expose the selected tubs. Material is then removed from these tubs by etching and material (24, 26) having a new resistivity value and/or conductivity type is grown in the empty tub regions.
摘要翻译： 已经开发了一种用于改变介电离子（DI）晶片中的选定的浴缸的电阻率值和/或电导率类型的方法。 在形成常规桶结构之后，晶片被图案化层（20）覆盖，图案化层被蚀刻以暴露所选择的桶。 然后通过蚀刻从这些桶中取出材料，并且在空桶区域中生长具有新电阻率值和/或导电类型的材料（24,26）。
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