公开(公告)号：EP0388565B1

公开(公告)日：1996-06-05

申请号：EP89400830.9

申请日：1989-03-24

申请人： SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.)

发明人： MIller, Robert Otis ,  Liou, Fu-Tai

IPC分类号： H01L21/285 ,  H01L21/324 ,  H01L21/28

CPC分类号： H01L29/66575 ,  H01L21/28052 ,  H01L21/28518 ,  Y10S148/015 ,  Y10S148/019 ,  Y10S148/147

公开(公告)号：EP0435392B1

公开(公告)日：1995-10-04

申请号：EP90203382.8

申请日：1990-12-18

申请人： Philips Electronics N.V.

发明人： Jonkers, Alexander Gijsbertus Mathias ,  Seams, Christopher Alan ,  Godon, Harald ,  Stolmeijer, André

IPC分类号： H01L21/285 ,  H01L21/60

CPC分类号： H01L21/76895 ,  H01L21/28518 ,  Y10S148/019

公开(公告)号：EP0400821B1

公开(公告)日：1994-12-14

申请号：EP90304926.0

申请日：1990-05-08

申请人： SGS-THOMSON MICROELECTRONICS, INC.

发明人： Liou, Fu-Tai ,  Lin, Yih-Shung ,  Chen, Fusen E.

IPC分类号： H01L29/62 ,  H01L21/60

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L21/32155 ,  H01L21/76895 ,  H01L23/53271 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S148/015 ,  Y10S148/019 ,  Y10S148/02 ,  H01L2924/00

公开(公告)号：EP0589159A3

公开(公告)日：1994-11-09

申请号：EP93111016.7

申请日：1993-07-09

申请人： MOTOROLA, INC.

发明人： Cherniawski, Michael ,  Kaushik, Vidya S. ,  Barker, Jeffrey M. ,  Pyle, Ronald E.

IPC分类号： H01L21/28 ,  H01L21/285

CPC分类号： H01L23/485 ,  H01L21/76838 ,  H01L2924/0002 ,  Y10S148/019 ,  H01L2924/00

摘要： An electrical contact (46) to a phosphorous doped polysilicon gate electrode (18) is formed by preventing arsenic, from a source and drain implant, from doping a portion (22) of the polysilicon gate electrode (18). A photoresist mask (20) covers a portion (22) of the polysilicon gate electrode (18) during the implant, thus preventing it from being doped. An electrical contact (46) is then formed to the masked portion (22) of the polysilicon gate electrode (18).

摘要翻译： 与磷掺杂的多晶硅栅极电极（18）的电接触（46）通过防止来自源极和漏极注入的砷掺杂多晶硅栅极电极（18）的一部分（22）而形成。 光刻胶掩模（20）在注入期间覆盖多晶硅栅极电极（18）的一部分（22），从而防止其被掺杂。 然后将电触点（46）形成到多晶硅栅极电极（18）的掩模部分（22）。

公开(公告)号：EP0622844A1

公开(公告)日：1994-11-02

申请号：EP94303007.2

申请日：1994-04-26

申请人： SGS-THOMSON MICROELECTRONICS, INC.

发明人： Hodges, Robert Louis

IPC分类号： H01L21/90 ,  H01L21/82 ,  H01L21/285

CPC分类号： H01L27/11 ,  H01L21/28525 ,  H01L21/76889 ,  Y10S148/019

摘要： A thin film transistor structure having a first and a second polycrystalline silicon layer (36,40) of different conductivity types (P and N) has a high resistance contact at the resultant P-N junction (42). This contact resistance is reduced by forming TiSi₂ (titanium disilicide) or other refractory metal silicides (56) such as cobalt or molybdenum in specific regions, namely the P-N junction contact. Titanium disilicide consumes the portion of the second polycrystalline silicon layer (40) in the P-N contact junction (42) and at the same time consumes a small portion of the underlying first polycrystalline silicon layer (36), such that the high resistance P-N junction (42) now no longer exists.

摘要翻译： 具有第一和不同导电型的第二多晶硅层（36,40）（P和N）的薄膜晶体管结构具有在所得到的P-N结（42）的高电阻接触。 如钴或钼中的特定区域，即P-N结的接触：该接触电阻，通过形成的TiSi2（二硅化钛）或其它难熔金属硅化物（56）减小。 二硅化钛消耗在PN结接触（42）的第二多晶硅层（40）的部分，并且在所述的Sametime消耗下面的第一多晶硅层（36）没有检测高电阻PN结的一小部分（ 42）现在已经不再存在。

公开(公告)号：EP0526043A1

公开(公告)日：1993-02-03

申请号：EP92306496.8

申请日：1992-07-15

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kunishima,Iwao, c/o Intellectual Property Div. ,  Suguro, Kyoichi, c/o Intellectual Property Div.

IPC分类号： H01L21/285

CPC分类号： H01L29/66575 ,  H01L21/28518 ,  H01L29/456 ,  Y10S148/019 ,  Y10S148/147

摘要： According to this invention, a method of manufacturing a semiconductor device includes the steps of forming an impurity diffusion layer (17) of a second conductivity type on a semiconductor substrate (1) of a first conductivity type, forming a transition metal compound layer (21) containing a constituent element of the semiconductor substrate on the impurity diffusion layer (17), and doping an impurity of the second conductivity type in the metal compound layer by annealing in a reducing atmosphere. A semiconductor device includes a semiconductor substrate (1) of a first conductivity type, an impurity diffusion layer (17) of a second conductivity type formed in the semiconductor substrate (1) of the first conductivity type, and a conductive metal compound layer formed on the impurity diffusion layer (17), wherein the conductive metal compound layer consists of at least a transition metal, a semiconductor element, and an impurity element of the second conductivity type which is an impurity element of the second conductivity type, and the impurity element of the second conductivity in the conductive metal compound layer is uniformly distributed.

摘要翻译： 根据本发明，制造半导体器件的方法包括以下步骤：在第一导电类型的半导体衬底（1）上形成第二导电类型的杂质扩散层（17），形成过渡金属化合物层（21 ），在所述杂质扩散层（17）上含有所述半导体衬底的构成元素，并且通过在还原气氛中进行退火，在所述金属化合物层中掺杂所述第二导电类型的杂质。 半导体器件包括：第一导电类型的半导体衬底（1），形成在第一导电类型的半导体衬底（1）中的第二导电类型的杂质扩散层（17）和形成在第一导电类型的半导体衬底 所述杂质扩散层（17），其中所述导电金属化合物层至少由作为所述第二导电类型的杂质元素的第二导电类型的过渡金属，半导体元件和杂质元素组成，并且所述杂质元素 的导电性金属化合物层中的第二导电性均匀分布。

公开(公告)号：EP0404372A3

公开(公告)日：1991-03-06

申请号：EP90305951.7

申请日：1990-05-31

申请人： SGS-THOMSON MICROELECTRONICS, INC.

发明人： Spinner, Charles Ralph ,  Chen, Fusen E. ,  Liou, Fu-Tai

IPC分类号： H01L21/283 ,  H01L21/768

CPC分类号： H01L21/28525 ,  Y10S148/019 ,  Y10S148/147

摘要： A method for fabricating integrated circuits is used to improve contacts between polycrystalline interconnect and underlying polycrystalline or monocrystalline silicon regions. After contact openings are formed, a layer of titanium (48) is deposited over the integrated circuit. The titanium is reacted in nitrogen to form a silicide layer only in the openings. Titanium nitride and unreacted titanium are then removed, and a layer of polycrystalline silicon (56) deposited and patterned. The silicide (50, 51, 52) layer between the polycrystalline interconnect and the underlying silicon ensures that a high quality contact is formed.

公开(公告)号：EP0405979A2

公开(公告)日：1991-01-02

申请号：EP90307090.2

申请日：1990-06-28

申请人： RAYTHEON COMPANY

发明人： Feist, Wolfgang M.

IPC分类号： H01L21/331 ,  H01L21/60

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/8249 ,  Y10S148/01 ,  Y10S148/019

摘要： A base region (26) is implanted into an epitaxial layer (14). An emitter region (70) and a collector contact region (32) are formed of doped polysilicon on the epitaxial layer (14), the emitter region (30) being formed over the base region (26). The implant that forms the base region (26) extends below the surface of the epitaxial layer (14) in all regions not covered by the collector region (32). Low resistance silicide contacts (36,38,40,44), such as titanium or cobalt, are formed on the structure in a self-aligned fashion. The bipolar function transistor can be formed as part of BiCMOS circuitry.

摘要翻译： 将基极区域（26）注入到外延层（14）中。 发射极区（70）和集电极接触区（32）由外延层（14）上的掺杂多晶硅形成，发射极区（30）形成在基极区（26）上。 形成基极区域（26）的植入物在未被集电区域（32）覆盖的所有区域内延伸到外延层（14）的表面下方。 以自对准的方式在结构上形成低电阻硅化物触点（36,38,40,44），例如钛或钴。 双极性功能晶体管可以形成为BiCMOS电路的一部分。

公开(公告)号：EP0305143A3

公开(公告)日：1990-10-03

申请号：EP88307789.3

申请日：1988-08-23

申请人： FUJITSU LIMITED

发明人： Ohba, Takayuki

IPC分类号： H01L21/60 ,  H01L21/285 ,  C23C16/42

CPC分类号： H01L21/28562 ,  H01L21/76879 ,  Y10S148/019 ,  Y10S148/147

摘要： A method of selectively forming (growing or depositing) a conductor layer (7) on an exposed surface of a semiconductor substrate (2) or a conductor by using a metal halide gas and a silicon hydride gas at a ratio of a flow rate of the latter gas to that of the former gas (e.g., Si n H 2n+2 /WF₆) of 2 or less, and setting a growth temperature at 200°C or less. When a Si₃H₈ gas and a WF₆ gas, in particular, are used at the ratio of the flow rates (Si₃H₈/WF₆) of 1.0 or less, and the deposition temperature is set at 100°C to room temperature, a silicon-containing tungsten layer is selectively deposited (formed).

公开(公告)号：EP0388565A1

公开(公告)日：1990-09-26

申请号：EP89400830.9

申请日：1989-03-24

申请人： SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.)

发明人： MIller, Robert Otis ,  Liou, Fu-Tai

IPC分类号： H01L21/285 ,  H01L21/324 ,  H01L21/28

CPC分类号： H01L29/66575 ,  H01L21/28052 ,  H01L21/28518 ,  Y10S148/015 ,  Y10S148/019 ,  Y10S148/147

摘要： A process for forming a capping layer over a titanium silicide layer includes forming a layer of polysilicon (16) over a gate-oxide layer (14). A layer of titanium (18) is then formed over the poly layer (16) followed by deposition of a composite layer of tantalum silicide (20). The structure is then patterned and subjected to an annealing process to form a titanium silicide layer (22) covered by the capping layer (20) of tantalum silicide. The tantalum silicide provides a much higher oxidation resistant layer with the underlying titanium silicide providing the desirable conductive properties needed for long runs of interconnects on a semiconductor structure.

摘要翻译： 在硅化钛层上形成覆盖层的工艺包括在栅极 - 氧化物层（14）上形成多晶硅层（16）。 然后在多层（16）上形成一层钛（18），随后沉积硅化钽（20）的复合层。 然后对该结构进行构图，并进行退火处理以形成由硅化钽的覆盖层（20）覆盖的硅化钛层（22）。 硅化钽提供了更高的抗氧化层，底层的钛硅化物提供了在半导体结构上的长距离互连所需的理想导电性能。