公开(公告)号：EP1187194A3

公开(公告)日：2004-11-10

申请号：EP01307575.9

申请日：2001-09-06

申请人： SANYO ELECTRIC CO. LTD

发明人： Takada, Tadayoshi ,  Kitamura, Osamu ,  Okawa, Shigeaki ,  Hata, Hirotsugu ,  Fujinuma, Chikao

IPC分类号： H01L21/8228 ,  H01L21/86 ,  H01L21/762

CPC分类号： H01L21/76297 ,  H01L21/76264 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/1203

摘要： A buried layer of a collector region and a buried layer of a collector taking-out region are formed at the same time at each epitaxial layer when the collector region and the collector taking-out region of the semiconductor integrated circuit device according to the invention. Each buried layer is diffused to connect, and etched in V-groove. By that, the collector region and collector taking-out region made thick in film are formed at the same time so as to realize the semiconductor integrated circuit device of high withstanding voltage.

公开(公告)号：EP0600436B1

公开(公告)日：2003-07-30

申请号：EP93119271.0

申请日：1993-11-30

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Malhi, Satwinder ,  Shen, Chi-Cheong ,  Kwon, Oh-Kyong

IPC分类号： H01L21/76 ,  H01L21/98

CPC分类号： H01L21/768 ,  H01L21/76297 ,  H01L23/36 ,  H01L23/53271 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP0721211A3

公开(公告)日：1996-12-27

申请号：EP96104114.2

申请日：1989-02-06

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Nakagawa, Akio, c/o Patent Div. K.K. Toshiba ,  Furukawa, Kazuyoshi, c/o Patent Div. K.K. Toshiba ,  Ogura, Tsuneo, c/o Patent Div. K.K. Toshiba

IPC分类号： H01L21/76

CPC分类号： H01L21/76264 ,  H01L21/761 ,  H01L21/76275 ,  H01L21/76286 ,  H01L21/76297 ,  H01L21/763 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/7394 ,  Y10S148/012

摘要： A semiconductor device includes a semiconductor substrate, a pair of low breakdown voltage elements formed in the substrate so as to be adjacent to each other, and a high breakdown voltage element formed to be adjacent to one of the low breakdown voltage elements. The pair of low breakdown voltage elements are isolated from each other by a pn junction and the one of the low breakdown voltage elements and the high breakdown voltage element are isolated from each other by a dielectric material. The semiconductor substrate is a composite substrate formed by directly bonding a first substrate serving as an element region to a second substrate serving as a supporting member through an insulating film.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底中彼此相邻的一对低击穿电压元件，以及形成为与低击穿电压元件之一相邻的高击穿电压元件。 一对低击穿电压元件通过pn结彼此隔离，并且低击穿电压元件和高击穿电压元件之一通过电介质材料彼此隔离。 半导体衬底是通过绝缘膜将用作元件区域的第一衬底直接接合到用作支撑构件的第二衬底上形成的复合衬底。

公开(公告)号：EP0488344A3

公开(公告)日：1994-09-21

申请号：EP91120472.5

申请日：1991-11-29

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Moslehi, Mehrdad M.

IPC分类号： H01L21/76 ,  H01L21/20

CPC分类号： H01L21/76248 ,  H01L21/76297

摘要： This is a method of forming a semiconductor-on-insulator wafer with a single-crystal semiconductor substrate. Preferably the method comprises: anisotropically etching a substrate 22 to form trenches 24 having walls and bottoms; anisotropically depositing oxide 26,28,34 over a surface of the substrate 22 and on the trench 24 walls and bottoms; etching to remove trench wall oxide 28 , but leaving oxide 26,34 over the semiconductor surface 22 and on the trench 24 bottom, thereby creating seed holes which expose portions of the semiconductor substrate 22; epitaxially growing semiconductor material 32 on the exposed portions of the semiconductor substrate 22 to partially fill the trenches; depositing nitride; anisotropically etching the nitride to form nitride sidewalls 36; forming oxide 40 on top of the grown semiconductor material; removing nitride sidewalls 36; anisotropically etching semiconductor 42 until the buried oxide 34 is reached, thereby leaving islands of semiconductor material 44 on the buried oxide layer 34; thermally growing oxide 46 on areas of exposed semiconductor; anisotropically etching oxide 40 to expose the top of the semiconductor islands 44; and epitaxially growing semiconductor material 48 to merge the semiconductor islands 44 and create a layer of single-crystal semiconductor material which is insulated from the substrate 22. This is also a semiconductor-on-insulator wafer structure. The wafer comprises: trenches 24 having walls and bottoms in a single-crystal semiconductor substrate (e.g. silicon substrate 22 ; a first insulator (e.g. oxide 20,26,34) on a surface of the substrate and on the trench bottoms; a second insulator (e.g. oxide 46) on the trench walls; and a layer of single-crystal semiconductor material (e.g. silicon epilayer 48) on the surface and extending into the trenches, with the layer being insulated from the substrate.

公开(公告)号：EP0596414A2

公开(公告)日：1994-05-11

申请号：EP93117515.2

申请日：1993-10-28

申请人： HITACHI, LTD.

发明人： Sakurai, Naoki ,  Sugawara, Yoshitaka

IPC分类号： H01L21/76 ,  H01L21/74 ,  H01L29/06 ,  H01L21/762

CPC分类号： H01L29/7813 ,  H01L21/76297 ,  H01L27/0623 ,  H01L29/0611 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/7824 ,  H01L29/8611 ,  H01L2924/0002 ,  H02P6/085 ,  H01L2924/00

摘要： A semiconductor integrated circuit has a multilayered supporter (2, 22, 23) and one or more semiconductor islands (1) being disposed on the supporter (2, 22, 23) and being insulated against it by an insulating film (21). Within the islands (1), circuit elements are formed. The circuit further comprises an auxiliary electrode (33) provided at the supporter (2, 22, 23).

公开(公告)号：EP0142737B1

公开(公告)日：1993-10-06

申请号：EP84112839.0

申请日：1984-10-25

申请人： HARRIS CORPORATION

发明人： Short, John P. ,  McLachlan, Craig J. ,  Messmer, Charles ,  Reinecke, Paul S.

IPC分类号： H01L21/76 ,  H01L21/306

CPC分类号： H01L21/76297

公开(公告)号：EP0493116A2

公开(公告)日：1992-07-01

申请号：EP91312027.5

申请日：1991-12-24

申请人： SHIN-ETSU HANDOTAI COMPANY LIMITED

发明人： Ohta, Yutaka ,  Ohki, Konomu ,  Katayama, Masatake

IPC分类号： H01L21/76

CPC分类号： H01L21/76297 ,  Y10S438/928 ,  Y10S438/977

摘要： Single crystal silicon islands in a dielectric-separation substrate are separated completely and finished in a uniform thickness by preparatorily denuding a single crystal silicon substrate of a warpage suffered to occur therein.
This dielectric-separation substrate is produced by a method which comprises forming a thermal oxide film on a single crystal silicon substrate having grooves incised in advance therein, then forming an irreversibly thermally shrinkable film on the rear surface of said single crystal silicon substrate prior to depositing a polycrystalline silicon thereon, then depositing a polycrystalline silicon on said single crystal silicon substrate, and thereafter grinding said single crystal silicon substrate in conjunction with said irreversibly thermally shrinkable film.

摘要翻译： 电介质分离衬底中的单晶硅岛被完全分离，并通过对其中发生的翘曲的单晶硅衬底进行准备地剥蚀而以均匀的厚度完成。 该介电分离衬底通过包括在其上预先切割有凹槽的单晶硅衬底上形成热氧化膜，然后在沉积之前在所述单晶硅衬底的后表面上形成不可逆热收缩膜的方法 在其上沉积多晶硅，然后在所述单晶硅衬底上沉积多晶硅，然后与所述不可逆热收缩膜一起研磨所述单晶硅衬底。

公开(公告)号：EP0441270A2

公开(公告)日：1991-08-14

申请号：EP91101401.7

申请日：1991-02-02

申请人： HARRIS CORPORATION

发明人： Short, John Preston ,  McLachlan, Craig James ,  Rouse, George Vernon ,  Zibrida, James Robert

IPC分类号： H01L21/84

CPC分类号： H01L21/31654 ,  H01L21/2007 ,  H01L21/76251 ,  H01L21/76275 ,  H01L21/76297

摘要： A bonding method including pressing a pair of slices together with a liquid oxidant therebetween and subjecting the pair of slices to a temperature to bond the slices together. Preferably a liquid oxidant is applied to one of the slices before they are pressed together and then dried. The heating step for bonding is carried out at a sufficiently high temperature of at least 1100°C to make the slices pliable so as to comply with each other during the bonding step.

摘要翻译： 一种粘合方法，包括将一对切片与液体氧化剂一起压在其间并使一对切片经受将切片粘合在一起的温度。 优选地，在将它们压在一起然后干燥之前，将液体氧化剂施加到其中一个切片。 用于粘结的加热步骤在至少1100℃的足够高的温度下进行，以使切片在粘合步骤期间柔顺以便彼此相符。

公开(公告)号：EP0329309A3

公开(公告)日：1991-03-13

申请号：EP89301054.6

申请日：1989-02-03

申请人： AT&T Corp.

发明人： Easter, William Graham ,  Leffel, Daniel David

IPC分类号： H01L21/76

CPC分类号： H01L21/76297

摘要： A method has been developed for providing tub regions with various resistivities in a dielectrically isolated (DI) structure. The starting substrate material is etched to expose the locations designated for a resistivity modification, and epitaxial material of the modified resistivity value is used to fill the exposed tubs. The remainder of the fabrication process follows conventional DI fabrication techniques. The procedure may simply be used to create a DI structure containing both n-type and p-type tub regions. The idea may also be extended, however, to providing separate tubs with, for example, n+ resistivity, n- resistivity, p- resistivity and p+ resistivity, all within the same DI structure.

公开(公告)号：EP0328331A2

公开(公告)日：1989-08-16

申请号：EP89301137.9

申请日：1989-02-06

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Nakagawa, Akio c/o Patent Division ,  Furukawa, Kazuyoshi c/o Patent Division ,  Ogura, Tsuneo c/o Patent Division

IPC分类号： H01L21/76

CPC分类号： H01L21/76264 ,  H01L21/761 ,  H01L21/76275 ,  H01L21/76286 ,  H01L21/76297 ,  H01L21/763 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/7394 ,  Y10S148/012

摘要： A semiconductor device includes a semiconductor substrate, a pair of low breakdown voltage elements formed in the substrate so as to be adjacent to each other, and a high breakdown voltage element formed to be adjacent to one of the low breakdown voltage elements. The pair of low breakdown voltage elements are isolated from each other by a pn junction and the one of the low breakdown voltage elements and the high breakdown voltage element are isolated from each other by a dielectric material. The semiconductor substrate is a composite substrate formed by directly bonding a first substrate serving as an element region to a second substrate serving as a supporting member through an insulating film.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底中彼此相邻的一对低击穿电压元件，以及形成为与低击穿电压元件之一相邻的高击穿电压元件。 一对低击穿电压元件通过pn结彼此隔离，并且低击穿电压元件和高击穿电压元件之一通过电介质材料彼此隔离。 半导体衬底是通过绝缘膜将用作元件区域的第一衬底直接接合到用作支撑构件的第二衬底上形成的复合衬底。