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    PASSIVATION OF WIDE BAND-GAP BASED SEMICONDUCTOR DEVICES WITH HYDROGEN-FREE SPUTTERED NITRIDES
    3.
    发明公开
    PASSIVATION OF WIDE BAND-GAP BASED SEMICONDUCTOR DEVICES WITH HYDROGEN-FREE SPUTTERED NITRIDES 审中-公开
    ON BIG BAND基于距离的半导体元件的钝化与氢免费溅射氮化物

    公开(公告)号：EP1897128A1

    公开(公告)日：2008-03-12

    申请号：EP06785888.6

    申请日：2006-06-28

    申请人： CREE, INC.

    发明人： RING, Zoltan ,  HAGLEITNER, Helmut ,  HENNING, Jason, Patrick ,  MACKENZIE, Andrew ,  ALLEN, Scott, T. ,  SHEPPARD, Scott, Thomas ,  SMITH, Richard, Peter ,  SRIRAM, Saptharishi ,  WARD, Allan, III

    IPC分类号： H01L21/314 ,  H01L21/318

    摘要： A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.

    HYDROGEN MITIGATION SCHEMES IN THE PASSIVATION OF ADVANCED DEVICES
    4.
    发明公开
    HYDROGEN MITIGATION SCHEMES IN THE PASSIVATION OF ADVANCED DEVICES 审中-公开
    威士忌ER ER EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN

    公开(公告)号：EP2904641A1

    公开(公告)日：2015-08-12

    申请号：EP13774322.5

    申请日：2013-09-26

    申请人： Cree, Inc.

    发明人： HAGLEITNER, Helmut ,  RING, Zoltan

    IPC分类号： H01L29/778 ,  H01L29/66 ,  H01L23/31

    CPC分类号： H01L29/7787 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/66462 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of a Silicon Nitride (SiN) passivation structure for a semiconductor device are disclosed. In general, a semiconductor device includes a semiconductor body and a SiN passivation structure over a surface of the semiconductor body. In one embodiment, the SiN passivation structure includes one or more Hydrogen-free SiN layers on, and preferably directly on, the surface of the semiconductor body, a Hydrogen barrier layer on, and preferably directly on, a surface of the one or more Hydrogen-free SiN layers opposite the semiconductor body, and a Chemical Vapor Deposition (CVD) SiN layer on, and preferably directly on, a surface of the Hydrogen barrier layer opposite the one or more Hydrogen-free SiN layers. The Hydrogen barrier layer preferably includes one or more oxide layers of the same or different compositions. Further, in one embodiment, the Hydrogen barrier layer is formed by Atomic Layer Deposition (ALD).

    摘要翻译： 公开了用于半导体器件的氮化硅（SiN）钝化结构的实施例。 通常，半导体器件在半导体本体的表面上包括半导体本体和SiN钝化结构。 在一个实施例中，SiN钝化结构在半导体本体的表面上，优选地直接位于半导体本体的表面上，包含一个或多个无氢SiN层，在该一个或多个氢的表面上，优选直接位于该表面上的氢屏障层 - 与半导体本体相对的许多SiN层，以及位于与一个或多个无氢SiN层相对的氢阻挡层的表面上并且优选地直接位于其上的化学气相沉积（CVD）SiN层。 阻氢层优选包括一个或多个相同或不同组成的氧化物层。 此外，在一个实施方案中，通过原子层沉积（ALD）形成氢阻隔层。

    NITRIDE-BASED TRANSISTORS WITH A PROTECTIVE LAYER AND A LOW-DAMAGE RECESS AND METHODS OF FABRICATION THEREOF
    5.
    发明公开
    NITRIDE-BASED TRANSISTORS WITH A PROTECTIVE LAYER AND A LOW-DAMAGE RECESS AND METHODS OF FABRICATION THEREOF 有权
    与用于生产保护涂层损坏武器剪裁和工艺的基于氮化物TRANSISTORS

    公开(公告)号：EP1704597A1

    公开(公告)日：2006-09-27

    申请号：EP04789143.7

    申请日：2004-09-28

    申请人： CREE, INC.

    发明人： SHEPPARD, Scott T. ,  SMITH, Richard Peter ,  RING, Zoltan

    IPC分类号： H01L29/778 ,  H01L21/335

    CPC分类号： H01L29/66462 ,  H01L29/2003 ,  H01L29/7783

    摘要： Transistors are fabricated by forming a nitride-based semiconductor barrier layer on a nitride-based semiconductor channel layer and forming a protective layer on a gate region of the nitride-based semiconductor barrier layer. Patterned ohmic contact metal regions are formed on the barrier layer and annealed to provide first and second ohmic contacts. The annealing is carried out with the protective layer on the gate region. A gate contact is also formed on the gate region of the barrier layer. Transistors having protective layer in the gate region are also provided as are transistors having a barrier layer with a sheet resistance substantially the same as an as-grown sheet resistance of the barrier layer.

    METHOD OF FORMING VIAS IN SILICON CARBIDE AND RESULTING DEVICES AND CIRCUITS
    6.
    发明公开
    METHOD OF FORMING VIAS IN SILICON CARBIDE AND RESULTING DEVICES AND CIRCUITS 有权
    用于碳化硅及其部件和电路PRODUCING VIAS

    公开(公告)号：EP1273032A1

    公开(公告)日：2003-01-08

    申请号：EP01922909.5

    申请日：2001-03-30

    申请人： CREE, INC.

    发明人： RING, Zoltan

    IPC分类号： H01L21/04 ,  H01L23/522 ,  H01L21/768

    CPC分类号： H01L21/76898 ,  H01L21/0445 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device on a first surface of a silicon carbide substrate and with at least one metal contact for the device on the first surface of the substrate. The opposite, second surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished second surface of the silicon carbide substrate to define a predetermined location for a via that is opposite the device metal contact on the first surface; etching the desired via through the desired masked location until the etch reaches the metal contact on the first surface; and metallizing the via to provide an electrical contact from the second surface of the substrate to the metal contact and to the device on the first surface of the substrate.

    MULTILAYER DIFFUSION BARRIERS FOR WIDE BANDGAP SCHOTTKY BARRIER DEVICES
    10.
    发明公开
    MULTILAYER DIFFUSION BARRIERS FOR WIDE BANDGAP SCHOTTKY BARRIER DEVICES 审中-公开
    MULTI-LAYER扩散阻挡于大带隙肖特基器件

    公开(公告)号：EP2548229A1

    公开(公告)日：2013-01-23

    申请号：EP11756677.8

    申请日：2011-01-13

    申请人： Cree, Inc.

    发明人： MIECZKOWSKI, Van ,  HAGLEITNER, Helmut ,  RING, Zoltan

    IPC分类号： H01L29/66

    CPC分类号： H01L29/475 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

    摘要： Semiconductor Schottky barrier devices include a wide bandgap semiconductor layer, a Schottky barrier metal layer on the wide bandgap semiconductor layer and forming a Schottky junction, a current spreading layer on the Schottky barrier metal layer remote from the wide bandgap semiconductor layer and two or more diffusion barrier layers between the current spreading layer and the Schottky barrier metal layer. The first diffusion barrier layer reduces mixing of the current spreading layer and the second diffusion barrier layer at temperatures of the Schottky junction above about 300°C and the second diffusion barrier layer reduces mixing of the first diffusion barrier layer and the Schottky barrier metal layer at the temperatures of the Schottky junction above about 300°C.