公开(公告)号：EP2569803A1

公开(公告)日：2013-03-20

申请号：EP11781034.1

申请日：2011-05-03

申请人： Cree, Inc.

发明人： MIECZKOWSKI, Van ,  HAGLEITNER, Helmut ,  HABERERN, Kevin

IPC分类号： H01L29/78

CPC分类号： H01L29/66068 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/47 ,  H01L29/475 ,  H01L29/66871 ,  H01L29/7786 ,  H01L29/812 ,  H01L29/872

摘要： Schottky barrier semiconductor devices are provided including a wide bandgap semiconductor layer and a gate on the wide bandgap semiconductor layer. The gate includes a metal layer on the wide bandgap semiconductor layer including a nickel oxide (NiO) layer. Related methods of fabricating devices are also provided herein.

公开(公告)号：EP1897128A1

公开(公告)日：2008-03-12

申请号：EP06785888.6

申请日：2006-06-28

申请人： CREE, INC.

发明人： RING, Zoltan ,  HAGLEITNER, Helmut ,  HENNING, Jason, Patrick ,  MACKENZIE, Andrew ,  ALLEN, Scott, T. ,  SHEPPARD, Scott, Thomas ,  SMITH, Richard, Peter ,  SRIRAM, Saptharishi ,  WARD, Allan, III

IPC分类号： H01L21/314 ,  H01L21/318

摘要： A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.

公开(公告)号：EP2915187B1

公开(公告)日：2017-11-22

申请号：EP13786400.5

申请日：2013-10-29

申请人： Cree, Inc.

发明人： HAGLEITNER, Helmut ,  RADULESCU, Fabian ,  NAMISHIA, Daniel

IPC分类号： H01L21/285 ,  H01L29/47

CPC分类号： H01L21/28581 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/7787

公开(公告)号：EP2904641A1

公开(公告)日：2015-08-12

申请号：EP13774322.5

申请日：2013-09-26

申请人： Cree, Inc.

发明人： HAGLEITNER, Helmut ,  RING, Zoltan

IPC分类号： H01L29/778 ,  H01L29/66 ,  H01L23/31

CPC分类号： H01L29/7787 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/66462 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of a Silicon Nitride (SiN) passivation structure for a semiconductor device are disclosed. In general, a semiconductor device includes a semiconductor body and a SiN passivation structure over a surface of the semiconductor body. In one embodiment, the SiN passivation structure includes one or more Hydrogen-free SiN layers on, and preferably directly on, the surface of the semiconductor body, a Hydrogen barrier layer on, and preferably directly on, a surface of the one or more Hydrogen-free SiN layers opposite the semiconductor body, and a Chemical Vapor Deposition (CVD) SiN layer on, and preferably directly on, a surface of the Hydrogen barrier layer opposite the one or more Hydrogen-free SiN layers. The Hydrogen barrier layer preferably includes one or more oxide layers of the same or different compositions. Further, in one embodiment, the Hydrogen barrier layer is formed by Atomic Layer Deposition (ALD).

摘要翻译： 公开了用于半导体器件的氮化硅（SiN）钝化结构的实施例。 通常，半导体器件在半导体本体的表面上包括半导体本体和SiN钝化结构。 在一个实施例中，SiN钝化结构在半导体本体的表面上，优选地直接位于半导体本体的表面上，包含一个或多个无氢SiN层，在该一个或多个氢的表面上，优选直接位于该表面上的氢屏障层 - 与半导体本体相对的许多SiN层，以及位于与一个或多个无氢SiN层相对的氢阻挡层的表面上并且优选地直接位于其上的化学气相沉积（CVD）SiN层。 阻氢层优选包括一个或多个相同或不同组成的氧化物层。 此外，在一个实施方案中，通过原子层沉积（ALD）形成氢阻隔层。

公开(公告)号：EP1774577A2

公开(公告)日：2007-04-18

申请号：EP05803665.8

申请日：2005-06-30

申请人： CREE, INC.

发明人： WARD, Alan, III ,  HENNING, Jason, Patrick ,  HAGLEITNER, Helmut ,  WIEBER, Keith, Dennis

IPC分类号： H01L21/28 ,  H01L29/45

CPC分类号： H01L29/1608 ,  H01L21/0455 ,  H01L21/0485 ,  H01L29/45 ,  Y10S438/931

摘要： A method of producing an ohmic contact and a resulting ohmic contact structure are disclosed. The method includes the steps of forming a deposited film of nickel and silicon on a silicon carbide surface at a temperature below which either element will react with silicon carbide and in respective proportions so that the atomic fraction of silicon in the deposited film is greater than the atomic fraction of nickel, and heating the deposited film of nickel and silicon to a temperature at which nickel-silicon compounds will form with an atomic fraction of silicon greater than the atomic fraction of nickel but below the temperature at which either element will react with silicon carbide. The method can further include the step of annealing the nickel-silicon compound to a temperature higher than the heating temperature for the deposited film, and within a region of the phase diagram at which free carbon does not exist.

摘要翻译： 公开了一种制造欧姆接触和产生的欧姆接触结构的方法。 该方法包括以下步骤：在碳化硅表面上形成镍和硅的沉积膜，低于该温度时，任一元素将与碳化硅反应并以相应的比例使沉积膜中硅的原子比大于 将镍和硅的原子分数加热至镍 - 硅化合物形成的温度，其中硅原子比硅的原子分数大于镍的原子分数，但低于任一元素将与硅反应的温度 碳化物。 该方法还可以包括将镍硅化合物退火至高于沉积膜的加热温度的温度，并且在不存在游离碳的相图的区域内。

公开(公告)号：EP2915187A1

公开(公告)日：2015-09-09

申请号：EP13786400.5

申请日：2013-10-29

申请人： Cree, Inc.

发明人： HAGLEITNER, Helmut ,  RADULESCU, Fabian ,  NAMISHIA, Daniel

IPC分类号： H01L21/285 ,  H01L29/47

CPC分类号： H01L21/28581 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/7787

摘要： Embodiments of a Nickel-rich (Ni-rich) Schottky contact for a semiconductor device and a method of fabrication thereof are disclosed. Preferably, the semiconductor device is a radio frequency or power device such as, for example, a High Electron Mobility Transistor (HEMT), a Schottky diode, a Metal Semiconductor Field Effect Transistor (MESFET), or the like. In one embodiment, the semiconductor device includes a semiconductor body and a Ni-rich Schottky contact on a surface of the semiconductor body. The Ni-rich Schottky contact includes a multilayer Ni-rich contact metal stack. The semiconductor body is preferably formed in a Group III nitride material system (e.g., includes one or more Gallium Nitride (GaN) and/or Aluminum Gallium Nitride (AlGaN) layers). Because the Schottky contact is Ni-rich, leakage through the Schottky contact is substantially reduced.

摘要翻译： 公开了用于半导体器件的富镍（富Ni）肖特基接触的实施例及其制造方法。 优选地，半导体器件是射频或功率器件，例如高电子迁移率晶体管（HEMT），肖特基二极管，金属半导体场效应晶体管（MESFET）等。 在一个实施例中，半导体器件在半导体本体的表面上包括半导体本体和富Ni肖特基接触。 富Ni肖特基接触包括多层富Ni接触金属叠层。 优选地，半导体体形成为III族氮化物材料体系（例如，包括一个或多个氮化镓（GaN）和/或氮化铝镓（AlGaN）层）。 由于肖特基接触是富Ni，所以通过肖特基接触的泄漏显着降低。

公开(公告)号：EP1851787A1

公开(公告)日：2007-11-07

申请号：EP06721027.8

申请日：2006-02-22

申请人： CREE, INC.

发明人： ZOLTAN, Ring ,  SHEPPARD, Scott Thomas ,  HAGLEITNER, Helmut

IPC分类号： H01L21/04 ,  H01L21/768 ,  H01L21/335

CPC分类号： H01L21/76898 ,  H01L21/0445 ,  H01L21/3065 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/452 ,  H01L29/7787 ,  H01L29/812

摘要： A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished surface of the silicon carbide substrate to define a predetermined location for at least one via that is opposite the device metal contact on the uppermost surface of the epitaxial layer and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts. Finally, metallizing the via provides an electrical path from the first surface of the substrate to the metal contact and to the device on the second surface of the substrate.

摘要翻译： 用于结合到集成电路中以消除用于电连接的引线键合的半导体器件包括碳化硅衬底和在碳化硅衬底上的宽带隙半导体材料的至少一个外延层。 外延层包括下表面和与碳化硅衬底相对的上表面。 外延层上的触点限定外延层中的源极，栅极和漏极区域。 至少一个导电通孔延伸穿过碳化硅衬底和外延层，每个导电通孔终止于源极，栅极或漏极触点中的一个上，从而提供通过碳化硅衬底和外延层到源极的导电路径 ，门或漏接点。

公开(公告)号：EP1593166A2

公开(公告)日：2005-11-09

申请号：EP04707133.7

申请日：2004-01-30

申请人： Cree Inc.

发明人： SLATER, JR., David, B. ,  HAGLEITNER, Helmut

IPC分类号： H01L33/00 ,  H01L21/04

CPC分类号： H01L33/405 ,  H01L21/0485 ,  H01L33/20 ,  H01L33/34 ,  H01L2224/48091 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： Reflective ohmic contacts for n-type silicon carbide include a layer consisting essentially of nickel on the silicon carbide. The layer consisting essentially of nickel is configured to provide an ohmic contact to the silicon carbide, and to allow transmission therethrough of optical radiation that emerges from the silicon carbide. A reflector layer is on the layer consisting essentially of nickel, opposite the silicon carbide. A barrier layer is on the reflector layer opposite the layer consisting essentially of nickel, and a bonding layer is on the barrier layer opposite the reflector layer. It has been found that the layer consisting essentially of nickel and the reflector layer thereon can provide a reflective ohmic contact for silicon carbide that can have low ohmic losses and/or high reflectivity.

摘要翻译： 对于n型碳化硅反射欧姆接触包括一个层上的碳化硅基本上由镍组成的聚合物。 基本上由镍组成的层被配置为提供到欧姆接触碳化硅，并允许光辐射传输通过那里没有从碳化硅射出。 反射器层是镍基本上由，碳化硅相反的层上。 的阻挡层是基本上由镍组成的层相对的反射器层上，和一粘结层是所述反射器层相对的阻挡层上。 已经发现，模具DASS层基本上由镍和反射器层在其上可以提供碳化硅的反射欧姆接触也可具有低欧姆损耗和/或高反射率。

公开(公告)号：EP1897128B1

公开(公告)日：2019-11-20

申请号：EP06785888.6

申请日：2006-06-28

申请人： Cree, Inc.

发明人： RING, Zoltan ,  HAGLEITNER, Helmut ,  HENNING, Jason, Patrick ,  MACKENZIE, Andrew ,  ALLEN, Scott, T. ,  SHEPPARD, Scott, Thomas ,  SMITH, Richard, Peter ,  SRIRAM, Saptharishi ,  WARD, Allan, III

IPC分类号： H01L21/314 ,  H01L21/318 ,  H01L29/24

公开(公告)号：EP2823511A1

公开(公告)日：2015-01-14

申请号：EP13707966.1

申请日：2013-02-15

申请人： Cree, Inc.

发明人： HAGLEITNER, Helmut ,  SRIRAM, Saptharishi

IPC分类号： H01L29/47 ,  H01L29/778 ,  H01L29/872 ,  H01L21/285 ,  H01L29/20

CPC分类号： H01L29/475 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/452 ,  H01L29/7786 ,  H01L29/872

摘要： The present disclosure relates to a Schottky contact for a semiconductor device. The semiconductor device has a body formed from one or more epitaxial layers, which reside over a substrate. The Schottky contact may include a Schottky layer, a first diffusion barrier layer, and a third layer. The Schottky layer is formed of a first metal and is provided over at least a portion of a first surface of the body. The first diffusion barrier layer is formed of a silicide of the first metal and is provided over the Schottky layer. The third layer is formed of a second metal and is provided over the first diffusion barrier layer. In one embodiment, the first metal is nickel, and as such, the silicide is nickel silicide. Various other layers may be provided between or above the Schottky layer, the first diffusion barrier layer, and the third layer.

摘要翻译： 本公开涉及半导体器件的肖特基接触。 半导体器件具有由位于衬底上的一个或多个外延层形成的主体。 肖特基接触可以包括肖特基层，第一扩散阻挡层和第三层。 肖特基层由第一金属形成并且设置在主体的第一表面的至少一部分上。 第一扩散阻挡层由第一金属的硅化物形成，并且设置在肖特基层上。 第三层由第二金属形成，并且设置在第一扩散阻挡层上。 在一个实施例中，第一金属是镍，因此硅化物是硅化镍。 可以在肖特基层，第一扩散阻挡层和第三层之间或之上提供各种其它层。