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    LIGHT EMITTING DIODES INCLUDING BARRIER LAYERS/SUBLAYERS AND MANUFACTURING METHODS THEREFOR
    3.
    发明公开
    LIGHT EMITTING DIODES INCLUDING BARRIER LAYERS/SUBLAYERS AND MANUFACTURING METHODS THEREFOR 审中-公开
    白细胞介素BIBRIESESCHICHTEN UND HERSTELLUNGSVEFAHREN

    公开(公告)号：EP1523776A2

    公开(公告)日：2005-04-20

    申请号：EP03765562.8

    申请日：2003-07-15

    申请人： CREE, INC.

    发明人： SLATER, JR., David, B. ,  WILLIAMS, Bradley, E. ,  ANDREWS, Peter, S. ,  EDMOND, John, A. ,  ALLEN, Scott, T. ,  BHARATHAN, Jayesh

    IPC分类号： H01L33/00

    CPC分类号： H01L33/40 ,  H01L33/38 ,  H01L2933/0016

    摘要： Semiconductor light emitting devices, such as light emitting diodes, include a substrate, an epitaxial region on the substrate that includes a light emitting region such as a light emitting diode region, and a multilayer conductive Stack including a reflector layer, on the epitaxial region. A barrier layer is provided on the reflector layer and extending on a sidewall of the reflector layer. The multilayer conductive Stack can also include an ohmic layer between the reflector and the epitaxial region. The barrier layer further extends on a sidewall of the ohmic layer. The barrier layer can also extend onto the epitaxial region outside the multilayer conductive Stack. The barrier layer can be fabricated as a series of alternating first and second sublayers.

    摘要翻译： 诸如发光二极管的半导体发光器件包括衬底，在衬底上的包括诸如发光二极管区域的发光区域的外延区域和在外延区域上包括反射器层的多层导电堆叠。 阻挡层设置在反射器层上并在反射器层的侧壁上延伸。 多层导电叠层还可以包括在反射器和外延区之间的欧姆层。 阻挡层进一步在欧姆层的侧壁上延伸。 阻挡层还可以延伸到多层导电叠层外的外延区域上。 阻挡层可以制成一系列交替的第一和第二子层。

    SELF-ALIGNED FIELD-EFFECT TRANSISTOR FOR HIGH FREQUENCY APPLICATIONS
    4.
    发明授权
    SELF-ALIGNED FIELD-EFFECT TRANSISTOR FOR HIGH FREQUENCY APPLICATIONS 失效
    自对准场效应晶体管用于高频应用

    公开(公告)号：EP0782770B1

    公开(公告)日：2001-12-19

    申请号：EP95933112.5

    申请日：1995-09-15

    申请人： CREE, INC.

    发明人： ALLEN, Scott, T.

    IPC分类号： H01L29/812 ,  H01L29/161 ,  H01L29/24 ,  H01L29/47

    CPC分类号： H01L29/1608 ,  H01L29/41775 ,  H01L29/66068 ,  H01L29/8128

    摘要： A metal semiconductor field-effect transistor (MESFET) is disclosed that exhibits reduced source resistance and higher operating frequencies. The MESFET comprises an epitaxial layer of silicon carbide and a gate trench in the epitaxial layer that exposes a silicon carbide gate surface between two respective trench edges. A gate contact is made to the gate surface and with the trench further defines the source and drain regions of the transistor. Respective ohmic metal layers form ohmic contacts on the source and drain regions of the epitaxial layer, and the edges of the metal layers at the trench are specifically aligned with the edges of the epitaxial layer at the trench.

    PASSIVATION OF WIDE BAND-GAP BASED SEMICONDUCTOR DEVICES WITH HYDROGEN-FREE SPUTTERED NITRIDES
    5.
    发明公开
    PASSIVATION OF WIDE BAND-GAP BASED SEMICONDUCTOR DEVICES WITH HYDROGEN-FREE SPUTTERED NITRIDES 审中-公开
    ON BIG BAND基于距离的半导体元件的钝化与氢免费溅射氮化物

    公开(公告)号：EP1897128A1

    公开(公告)日：2008-03-12

    申请号：EP06785888.6

    申请日：2006-06-28

    申请人： CREE, INC.

    发明人： RING, Zoltan ,  HAGLEITNER, Helmut ,  HENNING, Jason, Patrick ,  MACKENZIE, Andrew ,  ALLEN, Scott, T. ,  SHEPPARD, Scott, Thomas ,  SMITH, Richard, Peter ,  SRIRAM, Saptharishi ,  WARD, Allan, III

    IPC分类号： H01L21/314 ,  H01L21/318

    摘要： A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.

    SILICON CARBIDE METAL-SEMICONDUCTOR FIELD EFFECT TRANSISTORS AND METHODS OF FABRICATING SILICON CARBIDE METAL-SEMICONDUCTOR FIELD EFFECT TRANSISTORS
    6.
    发明公开
    SILICON CARBIDE METAL-SEMICONDUCTOR FIELD EFFECT TRANSISTORS AND METHODS OF FABRICATING SILICON CARBIDE METAL-SEMICONDUCTOR FIELD EFFECT TRANSISTORS 审中-公开
    金属硅半导体场效应晶体管和方法的这种晶体管HERSTTELLUNG

    公开(公告)号：EP1285464A2

    公开(公告)日：2003-02-26

    申请号：EP01910781.2

    申请日：2001-02-15

    申请人： CREE, INC.

    发明人： ALLEN, Scott, T. ,  PALMOUR, John, W. ,  ALCORN, Terrence, S.

    IPC分类号： H01L29/24

    CPC分类号： H01L29/8128 ,  H01L21/7605 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66856 ,  H01L29/812

    摘要： SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided. Utilization of such a buffer layer may reduce output conductance by a factor of 3 and produce a 3db increase in power gain over SiC MESFETs with conventional p-type buffer layers. A ground contact may also be provided to the p-type buffer layer and the p-type buffer layer may be made of two p-type layers with the layer formed on the substrate having a higher dopant concentration. SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs. Also, source and drain ohmic contacts may be formed directly on the n-type channel layer, thus, the n+ regions need not be fabricated and the steps associated with such fabrication may be eliminated from the fabrication process. Methods of fabricating such SiC MESFETs and gate structures for SiC FETs as well as passivation layers are also disclosed.