公开(公告)号：EP1026286A3

公开(公告)日：2000-12-27

申请号：EP00101506.4

申请日：2000-01-26

申请人： EBARA CORPORATION ,  KABUSHIKI KAISHA TOSHIBA

发明人： Mishima, Koji ,  Nagai, Mizuki ,  Kimizuka, Ryoichi ,  Matsuda, Tetsuo ,  Kaneko, Hisashi

IPC分类号： C25D5/34 ,  C25D7/12 ,  C25D5/18 ,  H05K3/22

CPC分类号： C25D17/001 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H05K3/22 ,  H05K2203/0392 ,  H05K2203/122 ,  Y10S205/917

摘要： The present invention relates to a method and apparatus for separating out metal copper according to an electroplating of copper using, for example, a solution of copper sulfate to produce copper interconnections on a surface of a substrate. The substrate is brought into contact, at least once, with a processing solution containing at least one of organic substance and sulfur compound which are contained in a plating solution. Thereafter, the substrate is brought into contact with the plating solution to plate the substrate.

摘要翻译： 本发明涉及一种使用例如硫酸铜溶液在铜表面上分离掉铜的方法和装置，以产生铜互连。 使基板与包含在电镀液中的含有有机物质和硫化合物中的至少一种的处理液接触至少一次。 此后，使基板与电镀液接触以对基板进行平板化。

公开(公告)号：EP1193330A2

公开(公告)日：2002-04-03

申请号：EP01121793.2

申请日：2001-09-20

申请人： EBARA CORPORATION ,  Kabushiki Kaisha Toshiba

发明人： Kimura, Norio ,  Mishima, Koji ,  Kunisawa, Junji ,  Inoue, Hiroaki ,  Makino, Natsuki ,  Matsuda, Tetsuo ,  Kaneko, Hisashi

IPC分类号： C25D5/02 ,  C25D5/54 ,  C25D3/38 ,  C25D7/06 ,  C25D7/12

CPC分类号： C25D17/001 ,  C25D5/02 ,  C25D7/123 ,  C25D17/004 ,  C25D17/02

摘要： A substrate is plated with a metal film of uniform thickness only in a limited area thereof which is to be plated. A substrate plating apparatus has a substrate holder for holding a substrate and a plating cell for plating a portion of a surface, to be plated, of the substrate held by the substrate holder. The plating cell has an anode disposed so as to cover the portion of the surface, to be plated, of the substrate held by the substrate holder, a cathode for supplying a current to the surface, to be plated, of the substrate in such a state that the cathode is brought into contact with the substrate, a plating liquid supplying device for supplying a plating liquid between the anode and the surface, to be plated, of the substrate, and a power source for applying a voltage between the anode and the cathode.

摘要翻译： 基板上镀有均匀厚度的金属膜，仅在要镀覆的有限区域内。 基板电镀装置具有用于保持基板的基板保持器和用于镀覆被基板保持器保持的基板的待镀表面的一部分的电镀单元。 电镀单元具有阳极，该阳极设置成覆盖被基板保持器保持的基板的要被电镀的部分的阴极，该阴极用于向基板的待镀表面供电， 表示阴极与基板接触，用于在阳极和要被电镀的表面之间提供镀液的电镀液供给装置，以及用于在阳极和阳极之间施加电压的电源 阴极。

公开(公告)号：EP1026286A2

公开(公告)日：2000-08-09

申请号：EP00101506.4

申请日：2000-01-26

申请人： EBARA CORPORATION ,  KABUSHIKI KAISHA TOSHIBA

发明人： Mishima, Koji ,  Nagai, Mizuki ,  Kimizuka, Ryoichi ,  Matsuda, Tetsuo ,  Kaneko, Hisashi

IPC分类号： C25D5/34 ,  C25D7/12 ,  C25D5/18

CPC分类号： C25D17/001 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H05K3/22 ,  H05K2203/0392 ,  H05K2203/122 ,  Y10S205/917

摘要： The present invention relates to a method and apparatus for separating out metal copper according to an electroplating of copper using, for example, a solution of copper sulfate to produce copper interconnections on a surface of a substrate. The substrate is brought into contact, at least once, with a processing solution containing at least one of organic substance and sulfur compound which are contained in a plating solution. Thereafter, the substrate is brought into contact with the plating solution to plate the substrate.

摘要翻译： 本发明涉及一种通过使用例如硫酸铜溶液电镀铜来分离金属铜以在衬底表面上产生铜互连的方法和设备。 使基材与含有电镀液中含有的有机物和硫化合物中的至少一种的处理液接触至少一次。 之后，使衬底与电镀液接触以镀覆衬底。

公开(公告)号：EP0865083A2

公开(公告)日：1998-09-16

申请号：EP98107810.8

申请日：1990-07-02

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Hasunuma, Masahiko ,  Kaneko, Hisashi ,  Sawabe, Atsuhito ,  Kawanoue, Takashi ,  Kohanawa, Yoshiko ,  Komatsu, Shuichi

IPC分类号： H01L23/485 ,  H01L23/532 ,  H01L29/41

CPC分类号： H01L21/28556 ,  H01L21/32051 ,  H01L23/532 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53242 ,  H01L23/53247 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising a semiconductor substrate having active regions electrically isolated from each other on a predetermined surface thereof, and a single layer or multilayer electrode line arranged on said semiconductor substrate through an insulating layer, wherein at least one layer of said electrode line is close-packed plane oriented, and a full width at half maximum of a close-packed plane diffraction profile of θ-scan as a measure of an orientation distribution being less than 6°, and said full width at half maximum of the close-packed plane diffraction profile of θ-scan is measured by using X-ray diffraction.

摘要翻译： 一种半导体器件，包括在其预定表面上具有彼此电隔离的有源区的半导体衬底和通过绝缘层布置在所述半导体衬底上的单层或多层电极线，其中所述电极线的至少一层是接近的 取向平面取向，并且紧密堆积的平面衍射图的半峰全宽; - 作为取向分布的度量小于6°，并且所述紧密堆积的半宽度的全宽度 通过使用X射线衍射来测量＆thetas的平面衍射图; -scan。

公开(公告)号：EP0865083A3

公开(公告)日：1998-10-21

申请号：EP98107810.8

申请日：1990-07-02

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Hasunuma, Masahiko ,  Kaneko, Hisashi ,  Sawabe, Atsuhito ,  Kawanoue, Takashi ,  Kohanawa, Yoshiko ,  Komatsu, Shuichi

IPC分类号： H01L23/485 ,  H01L23/532 ,  H01L29/41

CPC分类号： H01L21/28556 ,  H01L21/32051 ,  H01L23/532 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53242 ,  H01L23/53247 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising a semiconductor substrate having active regions electrically isolated from each other on a predetermined surface thereof, and a single layer or multilayer electrode line arranged on said semiconductor substrate through an insulating layer, wherein at least one layer of said electrode line is close-packed plane oriented, and a full width at half maximum of a close-packed plane diffraction profile of θ-scan as a measure of an orientation distribution being less than 6°, and said full width at half maximum of the close-packed plane diffraction profile of θ-scan is measured by using X-ray diffraction.

摘要翻译： 一种半导体器件，包括具有在其预定表面上彼此电隔离的有源区的半导体衬底以及通过绝缘层布置在所述半导体衬底上的单层或多层电极线，其中所述电极线的至少一层接近 并且作为取向分布的量度的θ-扫描的密堆积平面衍射分布的半值宽度小于6°，并且所述密堆积平面的半值全宽度 通过使用X射线衍射来测量θ扫描的衍射分布。

公开(公告)号：EP0895288A2

公开(公告)日：1999-02-03

申请号：EP98203369.8

申请日：1990-07-02

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Hasunuma, Masahiko ,  Kaneko, Hisashi ,  Sawabe, Atsuhito ,  Kawanoue, Takashi ,  Kohanawa, Yoshiko ,  Komatus, Shuichi

IPC分类号： H01L23/532

CPC分类号： H01L21/28556 ,  H01L21/32051 ,  H01L23/532 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53242 ,  H01L23/53247 ,  H01L2924/0002 ,  H01L2924/00

摘要： The gist is that the close-packed plane of a single crystal forming an electrode line such as electrodes or lines of a semiconductor device whose active regions are reduced in size, i.e., highly integrated, is arranged parallel to the longitudinal direction of the line; or in the case of a polycrystalline electrode line, the angle formed between the normal line direction of the close-packed plane of its crystal grains and that of the electrode line is arranged to be 80° or less.

公开(公告)号：EP0865083B1

公开(公告)日：2007-03-07

申请号：EP98107810.8

申请日：1990-07-02

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Hasunuma, Masahiko ,  Kaneko, Hisashi ,  Sawabe, Atsuhito ,  Kawanoue, Takashi ,  Kohanawa, Yoshiko ,  Komatsu, Shuichi

IPC分类号： H01L23/485 ,  H01L23/532 ,  H01L29/41

CPC分类号： H01L21/28556 ,  H01L21/32051 ,  H01L23/532 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53242 ,  H01L23/53247 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1455388A1

公开(公告)日：2004-09-08

申请号：EP02788667.0

申请日：2002-11-27

申请人： TOKYO ELECTRON LIMITED ,  Kabushiki Kaisha Toshiba ,  IBIDEN CO., LTD.

发明人： Takekoshi, Kiyoshi, TOKYO ELECTRON AT LIMITED ,  Hosaka, Hisatomi, TOKYO ELECTRON AT LIMITED ,  Hagihara, Junichi, TOKYO ELECTRON AT LIMITED ,  Hatsushika, Kunihiko, TOKYO ELECTRON AT LIMITED ,  Usui, Takamasa ,  Kaneko, Hisashi ,  Hayasaka, Nobuo ,  Ido, Yoshiyuki

IPC分类号： H01L21/66

CPC分类号： G01R31/2862 ,  G01R1/0433 ,  G01R1/0491 ,  G01R31/2831 ,  G01R31/286 ,  G01R31/2865 ,  G01R31/2867 ,  G01R31/287 ,  G01R31/2886

摘要： A reliability evaluation test apparatus (10) of this invention includes a wafer storage section (12) which stores a wafer (W) in a state wherein the electrode pads of a number of devices formed on the wafer and the bumps of a contactor (11) are totally in electrical contact with each other. The wafer storage section (12) transmits/receives a test signal to/from a measurement section (15) and has a hermetic and heat insulating structure. The wafer storage section (12) has a pressure mechanism (13) which presses the contactor (11) and a heating mechanism (14) which directly heats the wafer (W) totally in contact with the contactor (11) to a predetermined high temperature. The reliability of an interconnection film and insulating film formed on the semiconductor wafer are evaluated under an accelerated condition.

摘要翻译： 本发明的可靠性评价试验装置（10）包括晶片储存部（12），其存储晶片（W）的状态，其中形成在晶片上的多个器件的电极焊盘和接触器（11 ）彼此完全电接触。 晶片存储部分（12）向/从测量部分（15）发送/接收测试信号，并具有密封和隔热结构。 晶片储存部分（12）具有压力接触器（11）的压力机构（13）和将与接触器（11）完全接触的晶片（W）直接加热至预定高温的加热机构（14） 。 在加速条件下评估形成在半导体晶片上的互连膜和绝缘膜的可靠性。

公开(公告)号：EP1455388B1

公开(公告)日：2008-05-07

申请号：EP02788667.0

申请日：2002-11-27

申请人： TOKYO ELECTRON LIMITED ,  KABUSHIKI KAISHA TOSHIBA ,  IBIDEN CO., LTD.

发明人： Takekoshi, Kiyoshi, TOKYO ELECTRON AT LIMITED ,  Hosaka, Hisatomi, TOKYO ELECTRON AT LIMITED ,  Hagihara, Junichi, TOKYO ELECTRON AT LIMITED ,  Hatsushika, Kunihiko, TOKYO ELECTRON AT LIMITED ,  Usui, Takamasa ,  Kaneko, Hisashi ,  Hayasaka, Nobuo ,  Ido, Yoshiyuki

IPC分类号： H01L21/66 ,  G01R31/28

CPC分类号： G01R31/2862 ,  G01R1/0433 ,  G01R1/0491 ,  G01R31/2831 ,  G01R31/286 ,  G01R31/2865 ,  G01R31/2867 ,  G01R31/287 ,  G01R31/2886

摘要： A reliability tester (10) comprises a wafer containing section (12) containing a wafer (W) in the state that electrode pads of many devices formed on the wafer are all in electrical contact with bumps of a contactor (11). This wafer containing section (12) transmits/receives test signals with a measuring section (15) and has a hermetic and heat-insulating structure. The wafer containing section (12) has a pressing mechanism (13) for pressing the contactor (11) and a heating mechanism (14) for directly heating the wafer (W) in all contact with the contactor (11) to a predetermined high temperature. Thus, this tester evaluates the reliability of a wiring film and that of an insulation film formed on the semiconductor wafer under an acceleration condition.

公开(公告)号：EP1696479A1

公开(公告)日：2006-08-30

申请号：EP06009917.3

申请日：2002-11-27

申请人： TOKYO ELECTRON LIMITED ,  KABUSHIKI KAISHA TOSHIBA ,  IBIDEN CO., LTD.

发明人： Takekoshi, Kiyoshi, TOKYO ELECTRON AT LIMITED ,  Hosaka, Hisatomi, TOKYO ELECTRON AT LIMITED ,  Hagihara, Junichi, TOKYO ELECTRON AT LIMITED ,  Hatsushika, Kunihiko, TOKYO ELECTRON AT LIMITED ,  Usui, Takamasa ,  Kaneko, Hisashi ,  Hayasaka, Nobuo ,  Ido, Yoshiyuki

IPC分类号： H01L21/66 ,  G01R31/28

CPC分类号： G01R31/2862 ,  G01R1/0433 ,  G01R1/0491 ,  G01R31/2831 ,  G01R31/286 ,  G01R31/2865 ,  G01R31/2867 ,  G01R31/287 ,  G01R31/2886

摘要： A reliability evaluation test apparatus (10) of this invention includes a wafer storage section (12) which stores a wafer (W) in a state wherein the electrode pads of a number of devices formed on the wafer and the bumps of a contactor (11) are totally in electrical contact with each other. The wafer storage section (12) transmits/receives a test signal to/from a measurement section (15) and has a hermetic and heat insulating structure. The wafer storage section (12) has a pressure mechanism (13) which presses the contactor (11) and a heating mechanism (14) which directly heats the wafer (W) totally in contact with the contactor (11) to a predetermined high temperature. The reliability of an interconnection film and insulating film formed on the semiconductor wafer are evaluated under an accelerated condition.

摘要翻译： 本发明的可靠性评价试验装置（10）包括晶片储存部（12），其存储晶片（W）的状态，其中形成在晶片上的多个器件的电极焊盘和接触器（11 ）彼此完全电接触。 晶片存储部分（12）向/从测量部分（15）发送/接收测试信号，并具有密封和隔热结构。 晶片储存部分（12）具有压力接触器（11）的压力机构（13）和将与接触器（11）完全接触的晶片（W）直接加热至预定高温的加热机构（14） 。 在加速条件下评估形成在半导体晶片上的互连膜和绝缘膜的可靠性。