公开(公告)号：EP3157060B1

公开(公告)日：2018-03-07

申请号：EP16196220.4

申请日：2011-12-16

申请人： Everspin Technologies, Inc.

发明人： NAGEL, Kerry ,  SMITH, Kenneth ,  HOSSAIN, Moazzem ,  AGGARWAL, Sanjeev

IPC分类号： H01L29/82

CPC分类号： H01L43/12 ,  H01L21/28568 ,  H01L21/32133 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76877 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

摘要： A conductive via for connecting between a digit line and one side of the magnetic device is positioned beneath, and aligned with, each magnetic device. Other contacts may satisfy the same design rules, using the same process step. An electrode formed on the conductive via is polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to at least a 45 nanometer node, a cell packing factor approaching 6F 2 , and a uniform thickness of material between the bit lines and the underlying memory elements.

公开(公告)号：EP3147957A1

公开(公告)日：2017-03-29

申请号：EP16191054.2

申请日：2012-10-01

申请人： Everspin Technologies, Inc.

发明人： AGGARWAL, Sanjev ,  NAGEL, Kerry ,  JANESKY, Jason

IPC分类号： H01L43/12 ,  G11C11/15

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

摘要： A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.

摘要翻译： 双隧道势垒磁性元件具有位于第一和第二隧道势垒之间的自由磁性层以及位于第二隧道势垒之上的电极。 两步蚀刻工艺允许在第一蚀刻之后在电极的侧壁和第二隧道势垒上形成封装材料，以防止在执行第二蚀刻以去除一部分自由层时损坏第一隧道势垒。

公开(公告)号：EP2761682A1

公开(公告)日：2014-08-06

申请号：EP12778548.3

申请日：2012-10-01

申请人： Everspin Technologies, Inc.

发明人： AGGARWAL, Sanjev ,  NAGEL, Kerry ,  JANESKY,Jason

IPC分类号： H01L43/12 ,  G11C11/15

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

摘要： A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.

摘要翻译： 双隧道屏障磁性元件具有位于第一和第二隧道屏障之间的自由磁性层和位于第二隧道屏障上的电极。 两步蚀刻工艺允许在进行第二次蚀刻以除去自由层的一部分之后，在第一次蚀刻之后，在电极的侧壁和第二隧道势垒上形成封装材料，以防止损坏第一隧道势垒。

公开(公告)号：EP2652791A2

公开(公告)日：2013-10-23

申请号：EP11849101.8

申请日：2011-12-16

申请人： Everspin Technologies, Inc.

发明人： NAGEL, Kerry ,  SMITH, Kenneth ,  HOSSAIN, Moazzem ,  AGGARWAL, Sanjeev

IPC分类号： H01L29/82

CPC分类号： H01L43/12 ,  H01L21/28568 ,  H01L21/32133 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76877 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

摘要： A conductive via for connecting between a digit line and one side of the magnetic device is positioned beneath, and aligned with, each magnetic device. Other contacts may satisfy the same design rules, using the same process step. An electrode formed on the conductive via is polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to at least a 45 nanometer node, a cell packing factor approaching 6F 2 , and a uniform thickness of material between the bit lines and the underlying memory elements.

公开(公告)号：EP4336991A1

公开(公告)日：2024-03-13

申请号：EP23191241.1

申请日：2019-08-22

申请人： Everspin Technologies, Inc.

发明人： AGGARWAL, Sanjeev ,  DESHPANDE, Sarin ,  NAGEL, Kerry ,  KARRE, Santosh

IPC分类号： H10N50/01 ,  H10B61/00

摘要： Fabrication of a magnetic memory element, including a via (125) in an interlevel dielectric layer (120), providing an electrical connection between an underlying metal region (110) and a magnetoresistive stack device, such as a magnetic tunnel junction (150), involves forming a transition metal layer (130) in the via by atomic layer deposition. The via optionally includes a tantalum-rich layer (140) above, and/or a cap layer (115) below, the transition metal layer, and may have a diameter less than or equal than a diameter of the magnetoresistive stack device.

公开(公告)号：EP2761682B1

公开(公告)日：2017-03-01

申请号：EP12778548.3

申请日：2012-10-01

申请人： Everspin Technologies, Inc.

发明人： AGGARWAL, Sanjev ,  NAGEL, Kerry ,  JANESKY,Jason

IPC分类号： H01L43/12 ,  G11C11/15

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

摘要： A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer.

公开(公告)号：EP4100952A1

公开(公告)日：2022-12-14

申请号：EP21708472.2

申请日：2021-02-02

申请人： Everspin Technologies, Inc.

发明人： IKEGAWA, Sumio ,  ALMASI, Hamid ,  SHIMON ,  NAGEL, Kerry ,  LEE, Han, Kyu

IPC分类号： G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

公开(公告)号：EP3157060A1

公开(公告)日：2017-04-19

申请号：EP16196220.4

申请日：2011-12-16

申请人： Everspin Technologies, Inc.

发明人： NAGEL, Kerry ,  SMITH, Kenneth ,  HOSSAIN, Moazzem ,  AGGARWAL, Sanjeev

IPC分类号： H01L29/82

CPC分类号： H01L43/12 ,  H01L21/28568 ,  H01L21/32133 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76877 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

摘要： A conductive via for connecting between a digit line and one side of the magnetic device is positioned beneath, and aligned with, each magnetic device. Other contacts may satisfy the same design rules, using the same process step. An electrode formed on the conductive via is polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to at least a 45 nanometer node, a cell packing factor approaching 6F 2 , and a uniform thickness of material between the bit lines and the underlying memory elements.

摘要翻译： 用于连接磁性装置的数字线和一侧的导电通孔位于每个磁性装置的下方并与其对齐。 其他联系人可以使用相同的设计规则，使用相同的流程步骤。 抛光形成在导电通孔上的电极，以消除起始于导电通孔的步骤功能或接缝，从而向上传播通过各种沉积层。 该集成方法允许将MRAM器件改进至至少45纳米节点，接近6F 2的单元封装因子以及位线和底层存储器元件之间的材料的均匀厚度。

公开(公告)号：EP2652791B1

公开(公告)日：2017-03-01

申请号：EP11849101.8

申请日：2011-12-16

申请人： Everspin Technologies, Inc.

发明人： NAGEL, Kerry ,  SMITH, Kenneth ,  HOSSAIN, Moazzem ,  AGGARWAL, Sanjeev

IPC分类号： H01L43/12

CPC分类号： H01L43/12 ,  H01L21/28568 ,  H01L21/32133 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76877 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

摘要： A conductive via for connecting between a digit line and one side of the magnetic device is positioned beneath, and aligned with, each magnetic device. Other contacts may satisfy the same design rules, using the same process step. An electrode formed on the conductive via is polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to at least a 45 nanometer node, a cell packing factor approaching 6F 2 , and a uniform thickness of material between the bit lines and the underlying memory elements.

摘要翻译： 用于连接数字线和磁性设备的一侧的导电通孔位于每个磁性设备的下方并与其对齐。 使用相同的工艺步骤，其他联系人可能会满足相同的设计规则。 在导电通孔上形成的电极被抛光，以消除源于导电通孔的台阶功能或接缝向上传播通过各种沉积层。 这种集成方法允许将MRAM器件的缩放比例提高到至少45纳米节点，单元填充因子接近6F2，并且在位线和底层存储器元件之间的材料厚度均匀。