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    MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE
    1.
    发明授权
    MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：EP2883239B8

    公开(公告)日：2018-02-14

    申请号：EP13802420.3

    申请日：2013-09-24

    申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

    发明人： FUJIWARA, Hirokazu ,  SOEJIMA, Narumasa

    IPC分类号： H01L21/04

    CPC分类号： H01L21/0485 ,  H01L21/30604 ,  H01L21/32133

    摘要： A manufacturing method of a semiconductor device includes: forming an electric metal layer by depositing metal as art electrode material on an inside of an opening of an insulating layer on a surface of an SiC semiconductor substrate; widening a gap between an inner wall surface in an opening formed in the insulating layer and the electrode metal layer by etching the insulating layer after the electrode metal layer is formed; and forming an ohmic contact between the electrode metal layer and the SiC semiconductor substrate by heating the SiC semiconductor substrate and the metal electrode layer after the insulating layer is etched.

    DECOUPLED VIA FILL
    2.
    发明公开
    DECOUPLED VIA FILL 审中-公开

    公开(公告)号：EP3238235A1

    公开(公告)日：2017-11-01

    申请号：EP14909243.9

    申请日：2014-12-23

    申请人： Intel Corporation

    发明人： SHUSTERMAN, Yuriy V. ,  GRIGGIO, Flavio ,  INDUKURI, Tejaswi K. ,  BRAIN, Ruth A.

    IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/203

    CPC分类号： H01L21/76877 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/76847 ,  H01L23/3171 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

    摘要： Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

    摘要翻译： 公开了用于提供分离的通孔填充的技术。 给定通路沟槽，将第一阻挡层共形地沉积到沟槽的底部和侧壁上。 第一金属填充物被毯式沉积到沟槽中。 随后使非选择性沉积凹陷，使得沟槽的仅一部分填充有第一金属。 先前沉积的第一阻挡层与第一金属一起被去除，由此再次暴露沟槽的上侧壁。 第二阻挡层共形地沉积到第一金属的顶部和现在重新暴露的沟槽侧壁上。 将第二金属填充物全面沉积到剩余的沟槽中。 可以根据需要进行平面化和/或蚀刻以用于随后的处理。 因此，提供了使用双金属工艺填充高纵横比通孔的方法。 但是请注意，第一和第二填充金属可以是相同的。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    3.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
    半导体器件和制造半导体器件的方法

    公开(公告)号：EP3136424A2

    公开(公告)日：2017-03-01

    申请号：EP16184770.2

    申请日：2016-08-18

    申请人： Renesas Electronics Corporation

    发明人： Arigane, Tsuyoshi ,  Hisamoto, Digh

    IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

    CPC分类号： H01L27/1157 ,  H01L21/28282 ,  H01L21/32133 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42368 ,  H01L29/66833 ,  H01L29/792

    摘要： A property of a semiconductor device having a non-volatile memory is improved. A semiconductor device, which has a control gate electrode part and a memory gate electrode part placed above a semiconductor substrate of a non-volatile memory, is configured as follows. A thick film portion is formed in an end portion of the control gate insulating film on the memory gate electrode part side, below the control gate electrode part. According to this configuration, even when holes are efficiently injected to a comer portion of the memory gate electrode part by an FN tunnel erasing method, electrons can be efficiently injected to the comer portion of the memory gate electrode part by an SSI injection method. Thus, a mismatch of the electron/hole distribution can be moderated, so that the retention property of the memory cell can be improved.

    摘要翻译： 具有非易失性存储器的半导体器件的特性得到改善。 具有控制栅极电极部分和设置在非易失性存储器的半导体衬底上方的存储器栅极电极部分的半导体器件如下配置。 在控制栅极电极部分下方的存储器栅极电极部分侧上的控制栅极绝缘膜的端部中形成厚膜部分。 根据该结构，即使通过FN隧道擦除法将空穴高效率地注入存储器栅极电极部的角部，也能够通过SSI注入法将电子高效率地注入存储器栅极电极部的角部。 因此，可以缓和电子/空穴分布的不匹配，从而可以提高存储单元的保持特性。

    Method of making a thin film transistor device
    6.
    发明公开
    Method of making a thin film transistor device 审中-公开
    一种用于制造薄膜晶体管器件的方法

    公开(公告)号：EP2709158A3

    公开(公告)日：2014-08-20

    申请号：EP13184571.1

    申请日：2013-09-16

    申请人： Hsieh, Incha

    发明人： Hsieh, Incha

    IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L27/12

    CPC分类号： H01L29/66757 ,  H01L21/32133 ,  H01L21/32139 ,  H01L27/1288 ,  H01L29/78621

    摘要： A method of making a thin film transistor device includes: forming a semiconductor layer (51), a dielectric layer (52), and a gate-forming layer (53) on the dielectric layer (52) to define a layered structure (50), forming a gray scale photoresist pattern (54) on the gate-forming layer (53), stripping the gray scale photoresist pattern (54) isotropically to cause removal of source and drain defining regions (542, 543), etching the gate-forming layer (53) anisotropically so as to remove source and drain covering region (532, 533), doping a first type dopant into source and drain regions (511, 512), and removing a gate defining region (541) from the gate-forming layer (53).