公开(公告)号：EP2416249A1

公开(公告)日：2012-02-08

申请号：EP09842570.5

申请日：2009-03-31

申请人： Fujitsu Limited

发明人： NAKAYAMA, Hiroshi ,  ICHIMIYA, Junji ,  ITOU, Daisuke ,  ITOZAWA, Shintaro

IPC分类号： G06F11/22

CPC分类号： G01R33/098 ,  B82Y25/00 ,  G01R31/31917 ,  G01R31/31922 ,  G01R33/093

摘要： A signal inversion unit inverts an adjustment pattern signal input as received data. A clock adjustment control circuit acquires a first TAP value adjusted and obtained when a phase adjusting operation is performed on a clock adjustment circuit in a state in which the adjustment pattern signal is not inverted, a first detection frequency of the adjustment pattern signal in a runtime of the operation, a second TAP value adjusted and obtained when the phase adjusting operation is performed in a state in which the adjustment pattern signal is inverted by the signal inversion unit, and a second detection frequency of the adjustment pattern signal in the runtime of the operation. A controller tests an operating state of the phase adjusting operation based on the first and second TAP values and the first and second detection frequencies of the adjustment pattern obtained by the clock adjustment control circuit.

摘要翻译： 信号反转单元反转作为接收数据输入的调整模式信号。 时钟调节控制电路获取当在调节模式信号未被反转的状态下对时钟调节电路执行相位调节操作时调节和获得的第一TAP值，运行时中的调节模式信号的第一检测频率 ，当在由信号反转单元反转调整图案信号的状态下执行相位调整操作时调整和获得的第二TAP值以及在运行时的调整图案信号的第二检测频率 操作。 控制器基于由时钟调节控制电路获得的调节图案的第一和第二TAP值以及第一和第二检测频率来测试相位调节操作的操作状态。

公开(公告)号：EP2405601A1

公开(公告)日：2012-01-11

申请号：EP09841095.4

申请日：2009-03-04

申请人： Fujitsu Limited

发明人： ITOZAWA, Shintaro ,  NAKAYAMA, Hiroshi ,  ICHIMIYA, Junji ,  ITOU, Daisuke

IPC分类号： H04L7/00

CPC分类号： H04L7/02 ,  G06F1/10 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/04

摘要： A transmission LSI calculates a buffer usage rate in accordance with data stored in a buffer in a transmission data processing unit and determines, in accordance with the calculated buffer usage rate, the number of signal lines that perform a phase readjustment and the timing thereof. Then, the transmission LSI and a receiving LSI perform a phase adjustment using some of the signal lines and continues a data transfer using the rest of the signal lines. Accordingly, it is possible to maintain the optimum phase of a clock without delaying the data transfer.

摘要翻译： 发送LSI根据存储在发送数据处理单元中的缓冲器中的数据来计算缓冲器使用率，并且根据计算的缓冲器使用率确定执行相位重新调整的信号线的数量及其定时。 然后，传输LSI和接收LSI使用一些信号线执行相位调整，并使用剩余的信号线继续进行数据传送。 因此，可以保持时钟的最佳相位而不延迟数据传送。

公开(公告)号：EP2624000A1

公开(公告)日：2013-08-07

申请号：EP10857801.4

申请日：2010-09-27

申请人： Fujitsu Limited

发明人： ITOZAWA, Shintaro ,  NISHIO, Masahiro ,  NAKAYAMA, Hiroshi ,  ICHIMIYA, Junji ,  TAKAHASHI, Jin

IPC分类号： G01R31/28 ,  H01L21/822 ,  H01L27/04

CPC分类号： G01R31/318544 ,  G01R31/318541 ,  G01R31/318586

摘要： Object
An objective is to provide an integrated circuit capable of performing an operation check test for a combination circuit present in sections that are not connected by a scan chain.
Solution Means
An integrated circuit includes a first signal processing circuit in which a plurality of first combination circuits and a plurality of scan FFs (Flip Flop) are connected in an order of a scan FF, a first combination circuit, and a scan FF; a second signal processing circuit including a second combination circuit different from the first combination circuit; a first selection circuit configured to select data from a scan FF on an input side of one of the plurality of first combination circuits or data from an input terminal of the second signal processing circuit, and to output the selected data to the second combination circuit; and a second selection circuit configured to select data from another one of the plurality of first combination circuits different from the one of the plurality of first combination circuits or data from the second combination circuit, and to output the selected data to the scan FF on an output side of the another one of the plurality of first combination circuits.

摘要翻译： 目的是提供一种集成电路，其能够对未由扫描链连接的部分中存在的组合电路进行操作检查测试。 解决方案装置集成电路包括第一信号处理电路，其中多个第一组合电路和多个扫描FF（触发器）以扫描FF，第一组合电路和扫描FF的顺序连接; 第二信号处理电路，包括与第一组合电路不同的第二组合电路; 第一选择电路，被配置为从所述多个第一组合电路之一的输入侧的扫描FF或来自所述第二信号处理电路的输入端的数据中选择数据，并将所选择的数据输出到所述第二组合电路; 以及第二选择电路，被配置为从与所述多个第一组合电路不同的所述多个第一组合电路中的另一个组合电路或来自所述第二组合电路的数据中选择数据，并且将所选择的数据输出到所述扫描FF， 多个第一组合电路中的另一个的输出侧。

公开(公告)号：EP2288069A1

公开(公告)日：2011-02-23

申请号：EP08765097.4

申请日：2008-06-04

申请人： Fujitsu Limited

发明人： ITOZAWA, Shintaro ,  NAKAYAMA, Hiroshi ,  ICHIMIYA, Junji

IPC分类号： H04L1/22

CPC分类号： H04L1/007 ,  G06F11/0724 ,  G06F11/0763 ,  H04L1/0009 ,  H04L1/0057 ,  H04L25/14

摘要： A selection-signal generating circuit (106) in an LSI #1_(100) being a transmission-side LSI, when a transmission error is detected on an A-side signal line (301) (B-side signal line (302)) and degeneration control is performed thereon, instructs a selector (103) (selector (105)) to select an input from an ECC generator (102b) (ECC generator (104b)) in order to transmit data and ECC data for this data to be transmitted via the B-side signal line (302) (A-side signal line (301)), via the A-side signal line (301) (B-side signal line (302)). In this manner, the degenerated signal line is used to transmit the ECC data for transmission data to be transmitted via a signal line which is not degenerated, which allows error detection and error correction of the transmission data, and thus, reliability of the transmission data is improved and a transmission channel is prevented thereafter from being further degenerated.

摘要翻译： 当在A侧信号线（301）（B侧信号线（302））上检测到传输错误时，作为发送侧LSI的LSI＃1_（100）中的选择信号生成电路（106） 在其上执行退化控制，指示选择器（103）（选择器（105））选择来自ECC产生器（102b）（ECC产生器（104b））的输入，以便将该数据的数据和ECC数据发送为 通过A侧信号线（301）（B侧信号线（302））经由B侧信号线（302）（A侧信号线（301））发送。 以这种方式，退化信号线用于发送经由不退化的信号线发送的发送数据的ECC数据，其允许发送数据的错误检测和纠错，并且因此发送数据的可靠性 被改善，并且此后防止传输信道进一步退化。

公开(公告)号：EP2416249B1

公开(公告)日：2014-09-24

申请号：EP09842570.5

申请日：2009-03-31

申请人： Fujitsu Limited

发明人： NAKAYAMA, Hiroshi ,  ICHIMIYA, Junji ,  ITOU, Daisuke ,  ITOZAWA, Shintaro

IPC分类号： G06F11/22 ,  G06F11/263 ,  G01R31/319 ,  G01R33/09 ,  B82Y25/00

CPC分类号： G01R33/098 ,  B82Y25/00 ,  G01R31/31917 ,  G01R31/31922 ,  G01R33/093

公开(公告)号：EP2293199A1

公开(公告)日：2011-03-09

申请号：EP08764002.5

申请日：2008-06-03

申请人： Fujitsu Limited

发明人： NAKAYAMA, Hiroshi ,  ICHIMIYA, Junji ,  ITOZAWA, Shintaro

IPC分类号： G06F13/42

CPC分类号： G06F13/4072

摘要： A clock adjustment circuit 1022-j (j=1 through N) delays a phase of a clock signal on the basis of a TAP value j so as to output an adjusted clock signal j. By synchronizing transmission data with the adjusted clock signal j, reception data j [1:0] is generated. A data adjustment circuit 1031-j delays the transmission data on the basis of a TAP2 value j. By synchronizing the delayed transmission data with the adjusted clock signal j, adjusted reception data j [1:0] is generated. A data adjustment control circuit 1035-j generates the TAP2 value j on the basis of a result of a comparison between the reception data j [1:0] and the adjusted reception data j [1:0], and outputs to a clock adjustment control circuit 1023-j an instruction to update the TAP value j.

摘要翻译： 时钟调整电路1022-j（j = 1〜N）根据TAP值j延迟时钟信号的相位，输出调整后的时钟信号j。 通过使发送数据与调整后的时钟信号j同步，产生接收数据j [1：0]。 数据调整电路1031-j基于TAP2值j延迟发送数据。 通过将延迟的发送数据与调整后的时钟信号j进行同步，生成调整后的接收数据j [1：0]。 数据调整控制电路1035-j基于接收数据j [1：0]和调整后的接收数据j [1：0]的比较结果生成TAP2值j，并输出到时钟调整 控制电路1023-j更新TAP值j的指令。