公开(公告)号：EP2555242A1

公开(公告)日：2013-02-06

申请号：EP12178617.2

申请日：2012-07-31

申请人： Selex Sistemi Integrati S.p.A.

发明人： Chini, Alessandro ,  Lanzieri, Claudio

IPC分类号： H01L27/088 ,  H01L27/06 ,  H01L21/8252

CPC分类号： H01L27/0605 ,  H01L21/8252 ,  H01L27/0883 ,  H01L27/095 ,  H01L29/66545

摘要： The present invention concerns a layered epitaxial structure for enhancement/depletion PHEMT devices, an enhancement/depletion PHEMT device and a method for manufacturing an enhancement/depletion PHEMT device that finds advantageous, but not exclusive, application in the manufacturing of integrated circuits operating at millimetre-wave and microwave frequencies.

摘要翻译： 本发明涉及用于增强/消耗PHEMT器件的分层外延结构，增强/消耗PHEMT器件和用于制造增强/耗尽PHEMT器件的方法，其在制造以毫米为单位的集成电路的制造中发现有利但非排他的应用 波和微波频率。

公开(公告)号：EP1749313A2

公开(公告)日：2007-02-07

申请号：EP05763892.6

申请日：2005-05-19

申请人： Raytheon Company

发明人： HWANG, Kiuchul

IPC分类号： H01L21/8252 ,  H01L27/095

CPC分类号： H01L21/8252 ,  H01L27/095

摘要： A semiconductor structure with an enhancement mode transistor device disposed in a first region and depletion mode transistor device disposed in a laterally displaced second region. An enhancement mode transistor device InGaP etch stop/Schottky contact layer is disposed over a channel layer; a first layer different from InGaP disposed on the InGaP layer; a depletion mode transistor device etch stop layer is disposed on the first layer; and a second layer disposed on the depletion mode transistor device etch stop layer. The depletion mode transistor device has a gate recess passing through the second layer and the depletion mode transistor device etch stop layer and terminating in the first layer. The enhancement mode transistor device has a gate recess passing through the second layer, the depletion mode transistor device etch stop layer, the first layer, and terminating in the InGaP layer.

公开(公告)号：EP1676322A2

公开(公告)日：2006-07-05

申请号：EP04784553.2

申请日：2004-09-17

申请人： Spinnaker Semiconductor, Inc.

发明人： SNYDER, John, P. ,  LARSON, John, M.

IPC分类号： H01L27/095

CPC分类号： H01L29/66643 ,  H01L21/823814 ,  H01L27/095 ,  H01L29/7839

摘要： A Schottky barrier integrated circuit is disclosed, the circuit having at least one PMOS device or at least one NMOS device, at least one of the PMOS device or NMOS device having metal source-drain contacts forming Schottky barrier or Schottky-like contacts to the semiconductor substrate. The device provides a new distribution of mobile charge carriers in the bulk region of the semiconductor substrate, which improves device and circuit performance by lowering gate capacitance, improving effective carrier mobility, μ reducing noise, reducing gate insulator leakage, reducing hot carrier effect and improving reliability.

公开(公告)号：EP1238420A4

公开(公告)日：2004-08-18

申请号：EP00986434

申请日：2000-12-15

申请人： SPINNAKER SEMICONDUCTOR INC

发明人： SNYDER JOHN P

IPC分类号： H01L29/417 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/095 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L21/823835 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L27/095 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/7839 ,  H01L2924/0002 ,  H01L2924/00

摘要： A MISFEED device system and method of fabricating same are disclosed. The present invention utilizes Shotky barrier contacts (301, 302) for source and/or drain contact fabrication within the context of a MISFEED device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to control short channel effects. Additionally, the present invention unconditionally eliminates the parasitic bipolar gin associated with MISFEED fabrication, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art.

公开(公告)号：EP0899791A2

公开(公告)日：1999-03-03

申请号：EP98115325.7

申请日：1998-08-14

申请人： SILICONIX Incorporated

发明人： Williams, Richard K. ,  Darwish, Mohamed ,  Grabowski, Wayne ,  Korec, Jacek

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/095 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7806 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/872

摘要： The gate of a MOSFET is located in a lattice of trenches which define a plurality of cells. Most of the cells contain a MOSFET, but a selected number of the cells at predetermined locations in the lattice contain either a PN diode or a Schottky diode. The PN and Schottky diodes are connected in parallel with the channels in the MOSFET cells, with their anodes tied to the anode of the parasitic diodes in the MOSFET cells and their cathodes tied to the cathode of the parasitic diodes. When the MOSFET is biased in the normal direction (with the parasitic diode reverse-biased), the PN diodes provide a predictable breakdown voltage for the device and ensure that avalanche breakdown occurs at a location away from the trench gate where the hot carriers generated by the breakdown cannot damage the oxide layer which lines the walls of the trench. When the device is biased in the opposite direction, the Schottky diodes conduct and thereby limit charge storage at the PN junctions in the diode and MOSFET cells. This reduces the power loss in the MOSFET and improves the reverse recovery characteristics of the device when its bias is switched back to the normal direction.

摘要翻译： MOSFET的栅极位于限定多个单元的沟槽的格子中。 大多数单元包含MOSFET，但是格子中预定位置处的选定数量的单元格包含PN二极管或肖特基二极管。 PN和肖特基二极管与MOSFET单元中的通道并联连接，其阳极连接到MOSFET单元中的寄生二极管的阳极，其阴极连接到寄生二极管的阴极。 当MOSFET在正常方向（寄生二极管反向偏置）偏置时，PN二极管为器件提供可预测的击穿电压，并确保雪崩击穿发生在远离沟槽栅极的位置，其中热载流子由 击穿不能损伤沟槽壁的氧化物层。 当器件偏向相反方向时，肖特基二极管导通，从而限制二极管和MOSFET单元PN结处的电荷存储。 这降低了MOSFET中的功率损耗，并且当其偏压切换回法线方向时，可以提高器件的反向恢复特性。

公开(公告)号：EP0437702A3

公开(公告)日：1993-01-07

申请号：EP90122207.5

申请日：1990-11-20

申请人： FUJITSU LIMITED

发明人： Yokoyama, Teruo ,  Suzuki, Masahisa ,  Ishikawa, Tomonori ,  Igarashi, Takeshi

IPC分类号： H01L21/76 ,  H01L21/265

CPC分类号： H01L29/20 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/02631 ,  H01L21/7605 ,  H01L27/095 ,  H01L29/1075 ,  H01L29/32

摘要： A semiconductor integrated circuit including therein a plurality of active devices (44a, 44b) comprises a semiconductor substrate (22), a first buffer layer (24) on the substrate, a second buffer layer (26) provided on the substrate and incorporating therein defects with a concentration level substantially larger than the concentration level of the defects in the first buffer layer; a device layer (36) provided on the second buffer layer and being provided with the active devices, and a plurality of unconductive, device isolation regions (38) formed between the active devices such that the device isolation region extends from an upper surface of the device layer toward the substrate at least beyond a lower surface of the device layer.

公开(公告)号：EP0415768A2

公开(公告)日：1991-03-06

申请号：EP90309512.3

申请日：1990-08-30

申请人： FUJITSU LIMITED

发明人： Suzuki, Masahisa

IPC分类号： H01L23/485 ,  H01L27/095 ,  H01L21/28 ,  H01L29/41

CPC分类号： H01L29/66886 ,  H01L21/28587 ,  H01L21/28593 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/095 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate (10), an active layer (14) formed on the semiconductor substrate, source and drain electrodes (19, 20) respectively formed on the active layer, a gate electrode (31) formed on the active layer between the source and drain electrodes and including a gate contact portion (31a) which makes contact with the active layer and has a thickness greater than those of the source and drain electrodes and an overgate portion (31b) which is connected to the gate contact portion and extends over at least a portion of one of the source and drain electrodes, a first insulator layer (32) formed on the active layer and covering the source and drain electrodes and the gate contact portion, a first contact hole in the first insulator layer through which the overgate portion connects to the one of the source and drain electrodes, a second insulator layer (34) formed on the first insulator layer and covering the overgate portion, a second contact hole in the second insulator layer at a position above the overgate portion, and an interconnection layer (36) formed on the second insulator layer and connected to the overgate portion via the second contact hole.

摘要翻译： 一种半导体器件，包括：半导体衬底（10）形成在半导体衬底，源极和有源层（14）漏电极（19,20）分别形成在所述有源层上，形成在有源层上的栅电极（31） 源极和漏极电极和包括栅极接触部分（31A）其中，在其上连接至栅极接触部分栅极部分（31B）全部与所述有源层接触，并且具有厚度比源极和漏极电极的更大，并且在之间 和至少延伸在源极中的一个的部分和漏电极，形成在有源层和覆盖所述源极和漏极和栅极接触部分，在所述第一绝缘体层的第一接触孔上的第一绝缘层（32） 通过栅极上部分连接到形成在第一绝缘层和覆盖在栅极部分，第二接触孔在所述一个源极和漏极电极，第二绝缘层（34） 孔中在过栅极部上方的位置的第二绝缘体层，和形成在第二绝缘层上，并通过所述第二接触过的部分连接到所述栅极互连层（36）上。

公开(公告)号：EP0348944A2

公开(公告)日：1990-01-03

申请号：EP89111778.0

申请日：1989-06-28

申请人： NEC CORPORATION

发明人： Hida, Hikaru c/o NEC Corporation

IPC分类号： H01L27/06 ,  H01L27/095 ,  H01L21/82

CPC分类号： H01L27/095 ,  H01L21/8252 ,  H01L27/0605

摘要： The semiconductor device of the present invention includes a first transistor includes on one and the same substrate a first transistor having a first semiconductor layer with high-impurity density on which is provided a second semiconductor layer with low-impurity density, where the first semiconductor layer being of N type and having electron affinity greater than that of the second semiconductor layer, and is equipped with a control electrode provided on the second semiconductor layer and at least two ohmic electrodes that are electrically connected to the first semiconductor layer on both sides of the control electrode, and a second transistor having a third layer with low-impurity density provided on top of the second semiconductor layer on the first semiconductor layer, and is equipped with a control electrode provided on the third semiconductor layer and at least two ohmic electrodes that are electrically connected to the first semiconductor layer on both sides of the control electrode.
Further, by setting the first semiconductor layers to be a P-type semiconductor havin the sum of the electron affinity and the energy gap smaller than the sum of the electron affinity and the energy gap of the second semi­conductor layer, there can be obtained a semiconductor using holes as carriers.
The semiconductor device described above can be manufactured by sequentially gorwing crystals of the first, second, and third semiconductor layers on the substrate, selectively removing the third semiconductor layer, forming the first transistor on the second semiconductor layer in the removed part, and forming the second transistor on the third semiconductor layer in the portion other than the removed part of the third semiconductor layer.

摘要翻译： 本发明的半导体装置包括第一晶体管包括在一个和相同的基底上的所有具有高杂质浓度的第一半导体层，其与低杂质浓度，其中所述第一半导体层的第二半导体层的第一晶体管 N型的存在和具有电子亲和力比所述第二半导体层的更大的，并配有设置在所述第二半导体层上，并在至少两个欧姆电极做了控制电极电连接到所述第一半导体层上的bothsides 控制电极，并具有与设置在第一半导体层上的第二半导体层的顶部低杂质密度的第三层的第二晶体管，并且配备有设置在第三半导体层上，并在至少两个欧姆电极的控制电极做 电连接到所述第一半导体层上的控制EL的bothsides ectrode。 此外，通过设定第一半导体层是P型半导体就吃电子亲和力与能隙比电子亲和力和第二半导体层的能隙的总和较小的总和，可以得到一种半导体 使用孔作为载体。 以上描述的半导体器件可以通过依次gorwing所述第一，第二的晶体，和第三半导体层在基板上，选择性地去除所述第三半导体层，在除去部分中形成所述第二半导体层上的第一晶体管，以及在所述制造 在比所述第三半导体层的去除的部分以外的部分的第三半导体层上的第二晶体管。

公开(公告)号：EP0064370A3

公开(公告)日：1985-09-18

申请号：EP82302107

申请日：1982-04-23

申请人： FUJITSU LIMITED

发明人： MIMURA, TAKASHI

IPC分类号： H01L21/306 ,  H01L27/088 ,  H01L27/095 ,  H01L29/778 ,  H01L29/36 ,  H01L29/80

CPC分类号： H01L21/30621 ,  H01L27/0883 ,  H01L27/095 ,  H01L29/7787

公开(公告)号：EP0135307A2

公开(公告)日：1985-03-27

申请号：EP84305059.2

申请日：1984-07-25

申请人： TriQuint Semiconductor, Inc.

发明人： Rode, Ajit G.

IPC分类号： H01L21/28 ,  H01L29/80 ,  H01L29/04 ,  H01L21/306

CPC分类号： H01L29/66871 ,  H01L21/30617 ,  H01L21/8252 ,  H01L27/0883 ,  H01L27/095 ,  H01L29/045 ,  H01L29/812

摘要： Field effect transistors are manufactured using a substrate of compound semiconductor material by defining two gate areas which have their longitudinal dimensions so oriented with respect to the crystal axes of the substrate that the substrate material is more readily etchable through one of the gate areas than through the other gate area. The semiconductor material is etched through both the gate areas simultaneously with the same etchant, whereby gate recesses of different respective depths are formed in the substrate. Metal is deposited into the recesses.

摘要翻译： 使用化合物半导体材料的衬底制造场效应晶体管，通过限定两个栅极区域，它们的纵向尺寸相对于衬底的晶轴定向，使得衬底材料可以通过栅极区域之一更容易地蚀刻，而不是通过 其他门区。 半导体材料通过两个栅极区域与相同的蚀刻剂同时蚀刻，由此在衬底中形成不同相应深度的栅极凹槽。 金属沉积在凹槽中。