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    Semiconductor rectifier diode
    3.
    发明公开
    Semiconductor rectifier diode 失效
    Halbleitergleichrichterdiode。

    公开(公告)号：EP0103138A2

    公开(公告)日：1984-03-21

    申请号：EP83107656.7

    申请日：1983-08-03

    申请人： HITACHI, LTD.

    发明人： Naito, Masayoshi ,  Shimizu, Yoshiteru ,  Terasawa, Yoshio ,  Murakami, Susumu

    IPC分类号： H01L29/91

    CPC分类号： H01L29/861 ,  H01L29/0688 ,  H01L29/36

    摘要： in accordance with the present invention, there is provided a semiconductor rectifier diode which has low loss, quick response and soft reverse recovery properties and is composed of three consecutive layers, i.e., a p-type emitter layer (3), an n-type base layer (4) and an n-type emitter layer (5), the p-type emitter layer being composed of a first portion (31) and second portions (32) which surround said first portion, have a higher impurity concentration as compared with said first portion, and extend beyond said first portion toward said n-type base layer, and said base layer being composed of a first layer portion (41) which is adjacent to said n-type emitter layer and a second layer portion (42) which is located near a p-n junction (J,) side and has a lower impurity concentration as compared with said first layer portion.

    摘要翻译： 根据本发明，提供了一种具有低损耗，快速响应和软反向恢复性能的半导体整流二极管，由三层连续构成，即 例如，p型发射极层（3），n型基极层（4）和n型发射极层（5），p型发射极层由第一部分（31）和第二部分 围绕所述第一部分的部分（32）与所述第一部分相比具有更高的杂质浓度，并且延伸超过所述第一部分朝向所述n型基底层，并且所述基底层由第一层部分（41）组成， 其与所述n型发射极层相邻，第二层部分（42）位于pn结（J1）附近，并且与所述第一层部分相比具有较低的杂质浓度。

    Gate turn-off thyristor
    5.
    发明公开
    Gate turn-off thyristor 失效
    Thyristor mitLöschsteuerung。

    公开(公告)号：EP0022355A1

    公开(公告)日：1981-01-14

    申请号：EP80302258.1

    申请日：1980-07-03

    申请人： Hitachi, Ltd.

    发明人： Shimizu, Yoshiteru ,  Nagano, Takahiro ,  Sakurada, Shuroku ,  Ohta, Takehiro

    IPC分类号： H01L29/743

    CPC分类号： H01L29/0834 ,  H01L29/74 ,  H01L29/744

    摘要： The GTO thyristor consists of a semiconductor substrate 11 of disc shape which has, in sequence, an emitter layer 16 on the cathode side, a second base layer 15, a first base layer 13,14, and an emitter layer 12 on the anode side. The emitter layer on the anode side is short-circuited by an emitter short-circuiting layer 13. The emitter layer 16 on the cathode side is divided into a plurality of radially extending elongate units, and the emitter layer 12 on the anode side is likewise divided into elongate units which are provided in the portions located at the areas of projection of the units of the layer 16 onto the anode side. The emitter short-circuiting layer 13 thus forms a plurality of wedge-shaped regions between the said areas of projection of the units of the layer 16. A thyristor of high current capacity and quick turn-off is thus achieved because the varying distance from the central lead wire 20 of the control electrode 18 is compensated by the varying width of the said wedge shaped regions of the emitter short circuit layer 13.

    摘要翻译： GTO晶闸管由盘状半导体基板11构成，依次为阴极侧的发射极层16，第二基极层15，第一基极层13,14以及阳极侧的发射极层12 。 阳极侧的发射极层由发射极短路层13短路。阴极侧的发射极层16被分成多个径向延伸的细长单元，阳极侧的发射极层12也同样 分为细长单元，其设置在位于层16的单元的突出部分到阳极侧的部分中。 因此，发射极短路层13在层16的单元的所述投影区域之间形成多个楔形区域。因此，可以实现高电流容量和快速关断的晶闸管，因为距离 控制电极18的中心引线20被发射极短路层13的所述楔形区域的变化的宽度补偿。

    Gate turn-off thyristor
    7.
    发明公开
    Gate turn-off thyristor 失效
    门关闭三通阀

    公开(公告)号：EP0391337A3

    公开(公告)日：1991-04-24

    申请号：EP90106348.7

    申请日：1990-04-03

    申请人： HITACHI, LTD.

    发明人： Odai, Shingo ,  Sakurada, Shuroku ,  Ozeki, Toshiyuki ,  Sato, Yukimasa ,  Yatsuo, Tsutomu ,  Shimizu, Yoshiteru ,  Sanpei, Isamu ,  Yagishita, Kenji

    IPC分类号： H01L29/74 ,  H01L29/08

    CPC分类号： H01L29/0834 ,  H01L29/744

    摘要： A gate turn-off thyristor provided with a disc-shaped semiconductor substrate consisting of at least 4 layers of pnpn forming pn junctions between different layers adjacent to each other, in which the emitter layer (16) on the cathode side is divided into a plurality of elongated regions arranged in the radial direction and disposed in a plurality of rings, in which the base layer (14) on the anode side is formed so as to be connected partially with the anode electrode (2) disposed on the emitter layer on the anode side by a short-circuiting layer having the same conductivity type as the base layer and the short-circuiting layer described above has a coaxial circular pattern, characterized in that the short-circuiting layer described above is formed at least within the part, where the regions between different rings of the emitter layer on the cathode side are projected on the anode side.

    Gate turn-off thyristor
    8.
    发明公开
    Gate turn-off thyristor 失效
    闸极截止晶闸管。

    公开(公告)号：EP0391337A2

    公开(公告)日：1990-10-10

    申请号：EP90106348.7

    申请日：1990-04-03

    申请人： HITACHI, LTD.

    发明人： Odai, Shingo ,  Sakurada, Shuroku ,  Ozeki, Toshiyuki ,  Sato, Yukimasa ,  Yatsuo, Tsutomu ,  Shimizu, Yoshiteru ,  Sanpei, Isamu ,  Yagishita, Kenji

    IPC分类号： H01L29/74 ,  H01L29/08

    CPC分类号： H01L29/0834 ,  H01L29/744

    摘要： A gate turn-off thyristor provided with a disc-shaped semiconductor substrate consisting of at least 4 layers of pnpn forming pn junctions between different layers adjacent to each other, in which the emitter layer (16) on the cathode side is divided into a plurality of elongated regions arranged in the radial direction and disposed in a plurality of rings, in which the base layer (14) on the anode side is formed so as to be connected partially with the anode electrode (2) disposed on the emitter layer on the anode side by a short-circuiting layer having the same conductivity type as the base layer and the short-circuiting layer described above has a coaxial circular pattern, characterized in that the short-circuiting layer described above is formed at least within the part, where the regions between different rings of the emitter layer on the cathode side are projected on the anode side.

    摘要翻译： 一种栅极截止晶闸管，其设置有由至少4层pnpn组成的盘状半导体衬底，所述pnpn形成彼此相邻的不同层之间的pn结，其中阴极侧的发射极层（16）被分成多个 在多个环中布置的细长区域，其中阳极侧的基底层（14）形成为与设置在发射极层上的阳极电极（2）部分连接， 通过具有与基底层相同的导电类型的短路层和上述短路层的阳极侧具有同轴的圆形图案，其特征在于，上述短路层至少形成在该部分内，其中 阴极侧的发射极层的不同环之间的区域突出在阳极侧。

    A high breakdown voltage semiconductor device having a semi-insulating layer
    10.
    发明公开
    A high breakdown voltage semiconductor device having a semi-insulating layer 失效
    Halbleiterbauelement mit semi-isolierender Schichtfürhohe Durchbruchspannungen。

    公开(公告)号：EP0615291A1

    公开(公告)日：1994-09-14

    申请号：EP94301317.7

    申请日：1994-02-24

    申请人： HITACHI, LTD.

    发明人： Murakami, Susumu ,  Fukuda, Takuya ,  Shimizu, Yoshiteru ,  Sugawara, Yoshitaka

    IPC分类号： H01L29/06

    CPC分类号： H01L29/404 ,  H01L29/0626 ,  H01L29/408

    摘要： A semiconductor device has a first semiconductor region (13,15,17) of a first conductivity type and a second semiconductor region (14) of a second conductivity type contacted by respective first and second electrodes (6,2). A semi-insulating layer (8) extends between the first and second electrodes (6,2) and there is a first insulating (4,7) between the semi-insulating layer (8) and the first semiconductor region (13,15,17). The sheet resistivity of the semi-insulating layer (8) varies and this improves the high breakdown voltage of the p-n junction of the semiconductor device between the first and second semiconductor layers, by acting as a shield for charges included on a passivation insulation layer (19) covering the semi-insulating layer (8) and the first and second electrodes (6,2). Third semiconductor regions (16), with corresponding third electrodes (5) extend around, and are spaced from, the second semiconductor region (14). The third electrodes (5) extend over the parts of the first semiconductor region (13,15,17) adjacent the third semiconductor region (16) as this also improves the breakdown voltage. The second electrode (2) may also extend over the part of the first semiconductor region (13,15,17) adjacent the second semiconductor region (14) to cover the p-n junction therebetween.

    摘要翻译： 半导体器件具有第一导电类型的第一半导体区域（13,15,17）和由相应的第一和第二电极（6,2）接触的第二导电类型的第二半导体区域（14）。 半绝缘层（8）在第一和第二电极（6,2）之间延伸，并且在半绝缘层（8）和第一半导体区域（13,15）之间存在第一绝缘层（4,7） 17）。 半绝缘层（8）的薄层电阻率变化，这通过充当包含在钝化绝缘层上的电荷的屏蔽来改善半导体器件在第一和第二半导体层之间的pn结的高击穿电压（ 19）覆盖半绝缘层（8）和第一和第二电极（6,2）。 具有对应的第三电极（5）的第三半导体区域（16）围绕第二半导体区域（14）延伸并与之隔开。 第三电极（5）在与第三半导体区域（16）相邻的第一半导体区域（13,15,17）的部分上延伸，这也提高了击穿电压。 第二电极（2）也可以在与第二半导体区域（14）相邻的第一半导体区域（13,15,17）的一部分上延伸以覆盖它们之间的p-n结。