公开(公告)号：EP0338312A3

公开(公告)日：1990-03-21

申请号：EP89105833.1

申请日：1989-04-03

申请人： HITACHI, LTD.

发明人： Sakurai, Naoki ,  Mori, Mutsuhiro ,  Tanaka, Tomoyuki ,  Yasuda, Yasumichi ,  Nakano, Yasunori ,  Yatsuo, Tsutomu

IPC分类号： H01L29/72 ,  H01L29/08

CPC分类号： H01L29/0834 ,  H01L29/7398

摘要： An insulated gate bipolar transistor (IGBT) permits a large current to uniformly flow. A plurality of single crystal island regions (61) are formed in a supporting substrate (2) using dielectric films (1). Formed in each of the island regions are an n⁻ first region (61), a p second region (41) within the first region, an n⁺ third region (32) within the second region (41) and a p⁺⁺ fourth region (11) between the first region (61) and the dielectric film. All of these regions are exposed to the surface of the island region. Formed on the surface of the island region are a first main electrode (E) kept in ohmic contact with the second (41) and third (32) regions, a second main electrode (C) kept in ohmic contact with the fourth region (11) and a control electrode (G) located on the second (41) and third region (32) through an insulator (6).

摘要翻译： 绝缘栅双极晶体管（IGBT）允许大电流均匀流动。 使用介电膜（1）在支撑衬底（2）中形成多个单晶岛区（61）。 形成在每个岛区中的是第一区域（61），第一区域内的第二区域（41），第二区域（41）内的第三区域（32）和第四区域（第四区域 在第一区域（61）和电介质膜之间。 所有这些地区都暴露在岛屿地区的表面。 在岛区域的表面形成与第二区域（41）和第三区域（32）欧姆接触的第一主电极（E），与第四区域（11）保持欧姆接触的第二主电极 ）和通过绝缘体（6）位于第二区域（41）和第三区域（32）上的控制电极（G）。

公开(公告)号：EP0147776A2

公开(公告)日：1985-07-10

申请号：EP84115736.5

申请日：1984-12-18

申请人： HITACHI, LTD.

发明人： Yatsuo, Tsutomu ,  Nagano, Takahiro ,  Oikawa, Saburo ,  Sato, Yukimasa ,  Kimura, Shin ,  Fukui, Hirochi

IPC分类号： H01L29/60 ,  H01L29/10 ,  H01L29/08 ,  H01L29/74 ,  H01L29/72

CPC分类号： H01L29/744 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/1004 ,  H01L29/102 ,  H01L29/167 ,  H01L29/32 ,  H01L29/42304 ,  H01L29/42308

摘要： A gate turn-off thyristor and a transistor are disclosed, each of which comprises: a semiconductor substrate (1,101) including at least three semiconductor layers between a pair of principal surfaces, adjacent ones of the semiconductor layers being different in conductivity type from each other, a first one of the semiconductor layers being formed of at least one strip-shaped region (20, 120) with a constant width, a second one (30, 130) of the semiconductor layers being exposed to a first principal surface of the semiconductor substrate together with the strip-shaped region; a first main electrode (2.102) kept in ohmic contact with the strip-shaped region at the first principal surface; a first control electrode (3a, 103a) kept in ohmic contact with the second semiconductor layer (30, 130) on one side of the strip-shaped region in the direction of the width thereof and connected directly to a control terminal (6, 106); a second control electrode (3b, 103b) kept in ohmic contact with the second semiconductor layer on the other side of the strip-shaped region in the direction of the width thereof and connected to the control terminal through the first control electrode and the resistance (R) of the second semiconductor layer between the first control electrode and the second control electrode; a second main electrode (4. 104) kept in ohmic contact with a second principal surface of the semiconductor substrate; and means provided in the semiconductor substrate for accelerating the spatial biasing of a conductive region to the other side of the strip-shaped region in the direction of the width thereof when a current flowing across the semiconductor substrate is cut off, thereby enlarging the area of safety operation.

公开(公告)号：EP0066721A3

公开(公告)日：1983-09-14

申请号：EP82104076

申请日：1982-05-11

申请人： Hitachi, Ltd.

发明人： Nagano, Takahiro ,  Yatsuo, Tsutomu ,  Oikawa, Saburo ,  Fukui, Hiroshi ,  Kimura, Shin

IPC分类号： H01L29/743 ,  H01L29/10 ,  H01L29/08

CPC分类号： H01L29/74 ,  H01L29/1016 ,  H01L29/744

摘要： A gate turn-off thyristor is disclosed, which comprises semiconductor substrate (1) in which a cathode emitter layer (5), a first base layer (4), a second base layer (3), and an anode emitter layer (2) are formed in this order such that pn junctions are made between respective adjacent ones of the layers. The cathode emitter layer (5) are divided into portions each of which is exposed at one of the main surfaces of the semiconductor substrate (1), the anode emitter layer (2) is exposed to the other main surface thereof, each of the separated cathode emitter layer portions (5) is made in low resistance contact with an anode electrode (7) and the second base layer (3) has a thickness W nB [pm] determined by the condition: or where V BO [V] is a breakover voltage.

公开(公告)号：EP0181002A3

公开(公告)日：1988-09-21

申请号：EP85114227

申请日：1985-11-08

申请人： HITACHI, LTD.

发明人： Murakami, Susumu ,  Kagami, Teruyuki ,  Yatsuo, Tsutomu ,  Takahashi, Masaaki

IPC分类号： H01L29/40

CPC分类号： H01L29/405 ,  Y10S257/905

摘要： A semiconductor device includes a semiconductor substrate (100) having at least three semiconductor layers (1, 2, 3) of alternative different conductivity types between a pair of principal surfaces. A pair of main electrodes (6, 8) are kept in low-resistance contact with the outermost ones (1, 3) of the semiconductor layers. A surface-passivation insulating film (10) is provided on an exposed surface of the semiconductor substrate (100). A resistive material sheet (11) is provided on the insulating film (10) and connected electrically to semiconductor layers (1, 3) having their potentials substantially equal to the main electrodes (6, 8).

公开(公告)号：EP0180025A2

公开(公告)日：1986-05-07

申请号：EP85111807.5

申请日：1985-09-18

申请人： HITACHI, LTD.

发明人： Yasuda, Yasumichi ,  Tanaka, Tomoyuki ,  Nagano, Takahiro ,  Yatsuo, Tsutomu

IPC分类号： H01L27/06 ,  H01L29/52

CPC分类号： H01L27/0716 ,  H01L29/0692 ,  H01L29/7302

摘要： The present invention relates to a semiconductor device having complicated bipolar transistor and MOSFET. In an equivalent circuit of this semiconductor device, MOSFET (3) is connected between the base (33) and emitter (34) of the bipolar transistor (1). The bipolar transistor (1) is a vertical type transistor, and MOSFET (3) a lateral type transistor. The MOSFET (3) is formed on a base (33) surface on the side of one main surface on which the emitter (34) of the bipolar transistor (1) is exposed, in such a manner that the MOSFET (3) is substantially opposed to the emitter (34).

摘要翻译： 本发明涉及具有复杂的双极晶体管和MOSFET的半导体器件。 在该半导体器件的等效电路中，MOSFET（3）连接在双极晶体管（1）的基极（33）和发射极（34）之间。 双极晶体管（1）是垂直型晶体管，MOSFET（3）是侧向晶体管。 MOSFET（3）形成在一个主表面侧面上的基极（33）表面上，其中双极晶体管（1）的发射极（34）被暴露在其上，使得MOSFET（3）基本上 与发射极（34）相对。

公开(公告)号：EP0128268A1

公开(公告)日：1984-12-19

申请号：EP84102491.2

申请日：1984-03-08

申请人： HITACHI, LTD.

发明人： Kimura, Shin ,  Fukui, Hiroshi ,  Amano, Hisao ,  Yatsuo, Tsutomu ,  Oikawa, Saburo ,  Nagano, Takahiro

IPC分类号： H01L29/10 ,  H01L29/60 ,  H01L29/72 ,  H01L29/743

CPC分类号： H01L29/42304 ,  H01L29/42308

摘要： A semiconductor device such as a transistor or gate turn-off thyristor provided with a control electrode for improving the current cut-off performance, is disclosed in which an emitter layer (1d) of a semiconductor substrate is formed of a plurality of strip-shaped regions, a base layer (1c) adjacent to the strip-shaped regions is exposed to one principal surface of the semiconductor substrate together with the strip-shaped regions, one main electrode (2) is provided on each strip-shaped region, first and second control electrodes (3b, 3a) are provided on the base layer, on one and the other sides of each strip-shaped region viewed in the direction of the width thereof, respectively, the other main electrode is provided on the second principal surface of the semiconductor substrate, and a gate terminal (6) is not connected to the first control electrode (3b) but connected to the second control electrode (3a), in order to draw out carriers unequally by the first and second control electrodes at a turn-off period. At the initial stage of turn-off action, carriers are drawn out mainly by the second control terminal (3a), and a conductive region contracts so as to be limited to the first control electrode side. At the final stage of turn-off action, carriers are drawn out considerably by the first control electrode (3b), to complete the turn-off action.

公开(公告)号：EP0014098B1

公开(公告)日：1984-04-18

申请号：EP80300211.2

申请日：1980-01-23

申请人： Hitachi, Ltd.

发明人： Yatsuo, Tsutomu ,  Nagano, Takahiro

IPC分类号： H01L29/743 ,  H01L29/08

CPC分类号： H01L29/744

公开(公告)号：EP0066850A3

公开(公告)日：1983-08-17

申请号：EP82104878

申请日：1982-06-03

申请人： Hitachi, Ltd.

发明人： Yatsuo, Tsutomu ,  Nagano, Takahiro ,  Oikawa, Saburo ,  Horie, Akira

IPC分类号： H01L29/743 ,  H01L29/08

CPC分类号： H01L29/0839 ,  H01L29/74 ,  H01L29/744

摘要： A gate turn-off thyristor in which a cathode-emitter layer (2) is divided into a plurality of striplike regions which are radially arrayed on a major surface of a semiconductor substrate in a coaxial multi-ring pattern including a plurality of coaxially arrayed rings (R 1 , ..., R s ). The cathode-emitter strips (2) belonging to a given one of the rings have a same radial length. The cathode-emitter strips belonging to the inner ring of a coaxial multi-ring pattern have a smaller radial length than that of the cathode-emitter strips (2) constituting the outer ring. A cathode electrode (8) is contacted to the cathode-emitter strip (2) in low resistance ohmic contact. A gate electrode (9) is ohmic contacted with a low resistance to a cathode-base layer (3) located adjacent to the cathode-emitter strip (2) so as to enclose it. An anode electrode (7) is ohmic contacted with a low resistance to the anode-emitter layer (5). With the structure of GTO, turn-off operation of unit GTO's each including a cathode-emitter strip is equalized.

摘要翻译： 一种栅极关断晶闸管，其中阴极 - 发射极层（2）被划分成多个带状区域，所述多个带状区域以包括多个同轴排列的环的同轴多环图案的方式径向排列在半导体衬底的主表面上 （R1，...，Rs）。 属于给定的一个环的阴极 - 发射体条（2）具有相同的径向长度。 属于同轴多环图案的内环的阴极 - 发射极条具有比构成外环的阴极 - 发射极条（2）的径向长度更小的径向长度。 阴极电极（8）以低电阻欧姆接触与阴极 - 发射极条（2）接触。 栅极电极（9）与位于阴极 - 发射极条（2）附近的阴极 - 基极层（3）形成低阻抗的欧姆接触，以包围它。 阳极电极（7）与阳极 - 发射极层（5）的低电阻欧姆接触。 利用GTO的结构，均衡了包括阴极 - 发射极条的单元GTO的关断操作。

公开(公告)号：EP0066721A2

公开(公告)日：1982-12-15

申请号：EP82104076.3

申请日：1982-05-11

申请人： Hitachi, Ltd.

发明人： Nagano, Takahiro ,  Yatsuo, Tsutomu ,  Oikawa, Saburo ,  Fukui, Hiroshi ,  Kimura, Shin

IPC分类号： H01L29/743 ,  H01L29/10 ,  H01L29/08

CPC分类号： H01L29/74 ,  H01L29/1016 ,  H01L29/744

摘要： A gate turn-off thyristor is disclosed, which comprises semiconductor substrate (1) in which a cathode emitter layer (5), a first base layer (4), a second base layer (3), and an anode emitter layer (2) are formed in this order such that pn junctions are made between respective adjacent ones of the layers. The cathode emitter layer (5) are divided into portions each of which is exposed at one of the main surfaces of the semiconductor substrate (1), the anode emitter layer (2) is exposed to the other main surface thereof, each of the separated cathode emitter layer portions (5) is made in low resistance contact with an anode electrode (7) and the second base layer (3) has a thickness W nB [pm] determined by the condition: or
where V BO [V] is a breakover voltage.

摘要翻译： 公开了一种栅极截止晶闸管，其包括其中阴极发射极层（5），第一基极层（4），第二基极层（3）和阳极发射极层（2）的半导体衬底（1） 以这样的顺序形成，使得在相邻的相邻层之间形成pn结。 阴极发射极层（5）被分成在半导体衬底（1）的一个主表面上露出的部分，阳极发射极层（2）暴露于其另一个主表面， 阴极发射极层部分（5）被制成与阳极电极（7）的低电阻接触，并且第二基极层（3）具有由以下条件确定的厚度WnB：WnB> / = 3.817×10 < > <1> .VBO - 2.550×10 -4 .VBO 2 + 1.133×10 -7 .VBO 3 - 2.000×10 -1 <1>。 VBO 4或WnB> / = 3.200×10 <1> .VBO其中VBO [V]是破坏电压。

公开(公告)号：EP1033756A2

公开(公告)日：2000-09-06

申请号：EP00104286.0

申请日：2000-03-01

申请人： Hitachi, Ltd.

发明人： Onose, Hidekatsu ,  Yatsuo, Tsutomu ,  Ohno, Toshiyuki ,  Oikawa, Saburou

IPC分类号： H01L29/36 ,  H01L29/06 ,  H02M7/538

CPC分类号： H01L29/0615 ,  H02M7/003

摘要： In a semiconductor device such as a pn-junction diode, a Schottky diode, a JFET, a MOSFET or a MESFET, a drift layer is made of two layers, a first layer (12) and a second layer (13) having the same conductivity type as that of the first layer (12) and being disposed on said first layer (12), a termination region being formed on the surface of said second layer (13). The impurity concentration of the second layer (13) is less than half that of the first layer (12). The thickness of the second layer may moreover be made smaller than that of a main layer (14) of the device. In accordance with the above features, the field intensity is reduced at the termination region of the device.

摘要翻译： 在诸如pn结二极管，肖特基二极管，JFET，MOSFET或MESFET的半导体器件中，漂移层由两层制成，第一层（12）和具有该层的第二层（13） 导电类型与第一层（12）的导电类型相同，并且设置在所述第一层（12）上，终端区域形成在所述第二层（13）的表面上。 第二层（13）的杂质浓度小于第一层（12）的杂质浓度的一半。 另外可以使第二层的厚度小于装置的主层（14）的厚度。 根据上述特征，在设备的终端区域减小场强。