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    Microprocessor and method for setting up its peripheral functions
    2.
    发明公开
    Microprocessor and method for setting up its peripheral functions 失效
    微处理器和设置其外设功能的方法

    公开(公告)号：EP0740254A3

    公开(公告)日：1996-11-20

    申请号：EP96112686.9

    申请日：1990-12-07

    申请人： HITACHI, LTD. ,  HITACHI ULSI ENGINEERING CORPORATION

    发明人： Akao, Yasushi ,  Baba, Shiro ,  Miwa, Yoshiyuki ,  Sawase, Terumi ,  Sato, Yuji ,  Masumura, Shigeki

    IPC分类号： G06F13/12 ,  G06F9/38 ,  G06F15/78

    CPC分类号： G06F13/124 ,  G06F15/7814

    摘要： A single chip microprocessor 1 comprises a CPU 2 and a sub-processor 5 for implementing peripheral functions of the microprocessor 1 by software. The sub-processor 5 includes electrically writable internal storage devices called a microprogram memory unit 13 and a sequence control memory unit 62 for storing the software. Peripheral functions to be implemented by the sub-processor 5 can be defined or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define or modify the peripheral functions is the same as the time it takes to program the memory units 13 and 62. The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13 in addition to the microprogram memory unit 13 for providing microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information on what order the multiple address registers MAR0 to MAR11 are to be selected in sequentially. One of the address registers MAR0 to MAR11 is selected at every read cycle performed on the sequence control memory unit 62. A microaddress stored in the selected one of the address registers MAR0 to MAR11 is then supplied to the microprogram memory unit 13. Task null information can also be stored in the sequence control memory unit 62. The selection of one of the address registers MAR0 to MAR11 at every read cycle allows the sub-processor 5 to operate on an event driven basis.

    摘要翻译： 单片微处理器1包括一个CPU2和一个用于通过软件实现微处理器1的外围功能的子处理器5。 子处理器5包括称为微程序存储单元13的电可写内部存储设备和用于存储软件的顺序控制存储单元62。 可以通过将软件写入存储器单元13和62来定义或修改要由子处理器5实现的外围功能。因此，定义或修改外围功能所花费的时间与编程所花费的时间相同 存储器单元13和62.子处理器5还包括用于执行多个任务的执行单元16和用于向微程序存储单元13提供地址给微程序存储单元13以提供微指令的地址控制电路14 到执行单元16.序列控制存储器单元62是地址控制电路14的一部分，其也包括多个地址寄存器MAR0到MAR11。 序列控制存储单元62用于存储多个地址寄存器MAR0至MAR11将按顺序选择的顺序的信息。 在序列控制存储器单元62上执行的每个读取周期中选择地址寄存器MAR0至MAR11中的一个。然后，将存储在选择的地址寄存器MAR0至MAR11中的微型地址提供给微程序存储器单元13.任务空值信息 也可以存储在序列控制存储单元62中。在每个读取周期中选择地址寄存器MAR0至MAR11中的一个允许子处理器5以事件驱动为基础进行操作。

    Microprocessor and method for setting up its peripheral functions
    5.
    发明公开
    Microprocessor and method for setting up its peripheral functions 失效
    Mikroprozessor und Verfahren zur Aufstellung seiner Peripheriefunktionen

    公开(公告)号：EP0740254A2

    公开(公告)日：1996-10-30

    申请号：EP96112686.9

    申请日：1990-12-07

    申请人： HITACHI, LTD. ,  HITACHI ULSI ENGINEERING CORPORATION

    发明人： Akao, Yasushi ,  Baba, Shiro ,  Miwa, Yoshiyuki ,  Sawase, Terumi ,  Sato, Yuji ,  Masumura, Shigeki

    IPC分类号： G06F13/12 ,  G06F9/38 ,  G06F15/78

    CPC分类号： G06F13/124 ,  G06F15/7814

    摘要： A single chip microprocessor 1 comprises a CPU 2 and a sub-processor 5 for implementing peripheral functions of the microprocessor 1 by software. The sub-processor 5 includes electrically writable internal storage devices called a microprogram memory unit 13 and a sequence control memory unit 62 for storing the software. Peripheral functions to be implemented by the sub-processor 5 can be defined or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define or modify the peripheral functions is the same as the time it takes to program the memory units 13 and 62.
    The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13 in addition to the microprogram memory unit 13 for providing microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information on what order the multiple address registers MAR0 to MAR11 are to be selected in sequentially. One of the address registers MAR0 to MAR11 is selected at every read cycle performed on the sequence control memory unit 62. A microaddress stored in the selected one of the address registers MAR0 to MAR11 is then supplied to the microprogram memory unit 13. Task null information can also be stored in the sequence control memory unit 62. The selection of one of the address registers MAR0 to MAR11 at every read cycle allows the sub-processor 5 to operate on an event driven basis.

    摘要翻译： 单片微处理器1包括用于通过软件实现微处理器1的外围功能的CPU 2和子处理器5。 子处理器5包括称为微程序存储单元13的电可写内部存储装置和用于存储软件的顺序控制存储单元62。 可以通过将软件写入存储器单元13和62来定义或修改由子处理器5实现的外设功能。因此，定义或修改外设功能所花费的时间与编程所需的时间相同 子处理器5还包括用于执行多个任务的执行单元16和用于向微程序存储单元13提供地址的地址控制电路14，除了用于提供微指令的微程序存储单元13 序列控制存储器单元62是还包括多个地址寄存器MAR0至MAR11的地址控制电路14的一部分。 顺序控制存储器单元62用于存储关于要顺序地选择多地址寄存器MAR0至MAR11的顺序的信息。 在顺序控制存储器单元62上执行的每个读取周期选择地址寄存器MAR0至MAR11中的一个。然后将存储在所选择的一个地址寄存器MAR0至MAR11中的微地址提供给微程序存储单元13.任务空信息 也可以存储在顺序控制存储器单元62中。在每个读取周期选择地址寄存器MAR0至MAR11之一允许子处理器5在事件驱动的基础上操作。

    Microprocessor and method for setting up its peripheral functions
    7.
    发明公开
    Microprocessor and method for setting up its peripheral functions 失效
    用于设置其外围功能的微处理器和方法

    公开(公告)号：EP0431641A3

    公开(公告)日：1992-05-13

    申请号：EP90123577.0

    申请日：1990-12-07

    申请人： HITACHI, LTD. ,  HITACHI ULSI ENGINEERING CORPORATION

    发明人： Akao, Yasushi ,  Baba, Shiro ,  Miwa, Yoshiyuki ,  Sawase, Terumi ,  Sato, Yuji ,  Masumura, Shigeki

    IPC分类号： G06F13/12 ,  G06F13/00 ,  G06F15/78

    CPC分类号： G06F13/124 ,  G06F15/7814

    摘要： A single chip microprocessor l comprises a CPU 2 and a sub-processor 5 for implementing peripheral functions of the microprocessor l by software. The sub-processor 5 includes electrically writable internal storage devices called a microprogram memory unit l3 and a sequence control memory unit 62 for storing the software. Peripheral functions to be implemented by the sub-processor 5 can be defined or modified by writing software into the memory units l3 and 62. Accordingly, the time it takes to define or modify the peripheral functions is the same as the time it takes to program the memory units l3 and 62. The sub-processor 5 also includes an execution unit l6 for executing a plurality of tasks and an address control circuit l4 for providing addresses to the microprogram memory unit l3 in addition to the microprogram memory unit l3 for providing microinstructions to the execution unit l6. The sequence control memory unit 62 is part of the address control circuit l4 which also includes a plurality of address registers MAR0 to MARll. The sequence control memory unit 62 is used for storing information on what order the multiple address registers MAR0 to MARll are to be selected in sequentially. One of the address registers MAR0 to MARll is selected at every read cycle performed on the sequence control memory unit 62. A microaddress stored in the selected one of the address registers MAR0 to MARll is then supplied to the microprogram memory unit l3. Task null information can also be stored in the sequence control memory unit 62. The selection of one of the address registers MAR0 to MARll at every read cycle allows the sub-processor 5 to operate on an event driven basis.

    Microprocessor and method for setting up its peripheral functions
    8.
    发明公开
    Microprocessor and method for setting up its peripheral functions 失效
    Mikroprozessor und Verfahren zur Aufstellung seiner Peripheriefunktionen。

    公开(公告)号：EP0431641A2

    公开(公告)日：1991-06-12

    申请号：EP90123577.0

    申请日：1990-12-07

    申请人： HITACHI, LTD. ,  HITACHI ULSI ENGINEERING CORPORATION

    发明人： Akao, Yasushi ,  Baba, Shiro ,  Miwa, Yoshiyuki ,  Sawase, Terumi ,  Sato, Yuji ,  Masumura, Shigeki

    IPC分类号： G06F13/12 ,  G06F13/00 ,  G06F15/78

    CPC分类号： G06F13/124 ,  G06F15/7814

    摘要： A single chip microprocessor l comprises a CPU 2 and a sub-processor 5 for implementing peripheral functions of the microprocessor l by software. The sub-processor 5 includes electrically writable internal storage devices called a microprogram memory unit l3 and a sequence control memory unit 62 for storing the software. Peripheral functions to be implemented by the sub-processor 5 can be defined or modified by writing software into the memory units l3 and 62. Accordingly, the time it takes to define or modify the peripheral functions is the same as the time it takes to program the memory units l3 and 62.
    The sub-processor 5 also includes an execution unit l6 for executing a plurality of tasks and an address control circuit l4 for providing addresses to the microprogram memory unit l3 in addition to the microprogram memory unit l3 for providing microinstructions to the execution unit l6. The sequence control memory unit 62 is part of the address control circuit l4 which also includes a plurality of address registers MAR0 to MARll. The sequence control memory unit 62 is used for storing information on what order the multiple address registers MAR0 to MARll are to be selected in sequentially. One of the address registers MAR0 to MARll is selected at every read cycle performed on the sequence control memory unit 62. A microaddress stored in the selected one of the address registers MAR0 to MARll is then supplied to the microprogram memory unit l3. Task null information can also be stored in the sequence control memory unit 62. The selection of one of the address registers MAR0 to MARll at every read cycle allows the sub-processor 5 to operate on an event driven basis.

    摘要翻译： 单片微处理器l包括用于通过软件实现微处理器l的外围功能的CPU 2和子处理器5。 子处理器5包括称为微程序存储器单元13的电可写内部存储装置和用于存储软件的顺序控制存储单元62。 可以通过将软件写入存储器单元13和62来定义或修改由子处理器5实现的外设功能。因此，定义或修改外围功能所花费的时间与编程所需的时间相同 存储器单元13和62.除了用于提供微指令的微程序存储单元13之外，子处理器5还包括用于执行多个任务的执行单元16和用于向微程序存储单元13提供地址的地址控制电路14 到执行单元16。 顺序控制存储器单元62是还包括多个地址寄存器MAR0至MAR11的地址控制电路14的一部分。 序列控制存储器单元62用于存储关于多个地址寄存器MAR0至MAR11将被顺序选择的顺序的信息。 在顺序控制存储器单元62上执行的每个读取周期选择地址寄存器MAR0至MAR11中的一个。然后将存储在所选择的一个地址寄存器MAR0至MAR11中的微地址提供给微程序存储器单元13。 任务空信息也可以存储在顺序控制存储器单元62中。在每个读周期选择地址寄存器MAR0至MARll之一允许子处理器5在事件驱动的基础上操作。