利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

10 条记录 (耗时 0.012 秒)

    A compile type knowledge processing tool, a high-speed inference method therefor and a system using the tool
    4.
    发明公开
    A compile type knowledge processing tool, a high-speed inference method therefor and a system using the tool 失效
    知识处理工具编译型，高速推导方法，及使用该工具的系统。

    公开(公告)号：EP0380317A1

    公开(公告)日：1990-08-01

    申请号：EP90300732.6

    申请日：1990-01-24

    申请人： HITACHI, LTD.

    发明人： Kurosawa, Kenichi ,  Shimada, Masaru ,  Hirayama, Hirokazu ,  Bandoh, Tadaaki ,  Mori, Kiyomi

    IPC分类号： G06F17/30 ,  G06F9/44

    CPC分类号： G06N5/046 ,  G06N5/047

    摘要： High-speed inference method and system for a production system represented by an expert system. A knowledge base (16-3) comprised of a rule and a fact possessing a plurality of attributes is converted into machine language instructions executable by a processor (16-1) to execute inference. The machine language instruction of the fact has the function of transferring a value of the fact to a specified location and the machine language instruction of the rule has the function of performing matching decision by referring to the specified location. The number of pattern matching operations can be decreased and the interpretation overhead can be reduced to ensure high-speed inference.

    摘要翻译： 由一个规则和一个事实波塞的用于通过一个专家系统为代表的生产系统高速推理方法和系统。一个知识库（16-3）唱属性的多元性被转换为机器语言指令可由处理器执行（16- 1）来执行推断。 事实的机器语言指令具有传递环的函数的事实到指定的位置和该规则的机器语言指令的值具有通过参照指定的位置执行匹配决定的功能。 模式匹配操作的次数可以降低，并且可以降低解释开销，以确保高速推理。

    Parallel processing apparatus and parallel processing method
    6.
    发明公开
    Parallel processing apparatus and parallel processing method 失效
    并行处理装置和并行处理方法

    公开(公告)号：EP0407911A3

    公开(公告)日：1992-10-14

    申请号：EP90112939.5

    申请日：1990-07-06

    申请人： HITACHI, LTD.

    发明人： Kurosawa, Kenichi ,  Tanaka, Shigeya ,  Nakatsuka, Yasuhiro ,  Bandoh, Tadaaki

    IPC分类号： G06F9/38

    CPC分类号： G06F9/30189 ,  G06F9/30181 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

    摘要： The described parallel processing apparatus and method turns a processing state discrimination flag (PE, 116) off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit, when it executes successivc processing of conventional software, and when it executes parallel processing of new software turns the processing state discrimination flag (PE, 116) on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag (PE, 116) is added. The instructions are processed in one or in m arithmetic unit(s) (108, 109) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed.

    Parallel processing apparatus and parallel processing method
    9.
    发明公开
    Parallel processing apparatus and parallel processing method 失效
    Vorrichtung und Verfahren zur parallelen Verarbeitung。

    公开(公告)号：EP0407911A2

    公开(公告)日：1991-01-16

    申请号：EP90112939.5

    申请日：1990-07-06

    申请人： HITACHI, LTD.

    发明人： Kurosawa, Kenichi ,  Tanaka, Shigeya ,  Nakatsuka, Yasuhiro ,  Bandoh, Tadaaki

    IPC分类号： G06F9/38

    CPC分类号： G06F9/30189 ,  G06F9/30181 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

    摘要： The described parallel processing apparatus and method turns a processing state discrimination flag (PE, 116) off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit, when it executes successivc processing of conventional software, and when it executes parallel processing of new software turns the processing state discrimination flag (PE, 116) on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag (PE, 116) is added. The instructions are processed in one or in m arithmetic unit(s) (108, 109) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed.

    摘要翻译： 所描述的并行处理装置和方法使处理状态判别标志（PE，116）关闭，一次将程序数增加1，读出一个指令，并且在执行运算单元中的该指令时执行成功处理 常规软件，并且当执行新软件的并行处理时，处理状态判别标志（PE，116）打开，一次增加程序数量m，读出m个指令，并且通过m个算术对m个指令进行并行处理 单位。 为了选择上述两种处理之一，添加具有改变处理状态判别标志（PE，116）的功能的识别切换指令。 根据处理状态判别标志，在一个或多个运算单元（108,109）中对指令进行处理。 以这种方式，连续处理和并行处理具有兼容性并且被选择性地执行。

    Inference processing method and apparatus
    10.
    发明公开
    Inference processing method and apparatus 失效
    Verfahren und System zur Inferenzverarbeitung。

    公开(公告)号：EP0332427A2

    公开(公告)日：1989-09-13

    申请号：EP89302317.6

    申请日：1989-03-08

    申请人： HITACHI, LTD.

    发明人： Kurosawa, Kenichi ,  Shimada, Masaru ,  Bandoh, Tadaaki ,  Nakano, Toshihiko ,  Hayashi, Toshihiro

    IPC分类号： G06F9/44

    CPC分类号： G06N5/046

    摘要： A storage area (G5) for holding instantiation is provided together with a work area (G4) in order to rapidly generate a conflict set. When a condition of a rule is met, the instantiation of the rule is stored in the storage area in a form of data structure. The instantiation having an element whose attribute has been modified in an execution part of the rule is deleted (F2) from the conflict set.

    摘要翻译： 与工作区域（G4）一起提供用于保持实例化的存储区域（G5），以便快速生成冲突集。 当满足规则的条件时，规则的实例化以数据结构的形式存储在存储区域中。 具有在规则的执行部分中其属性被修改的元素的实例被从冲突集中删除（F2）。