公开(公告)号：EP2232548A4

公开(公告)日：2013-02-27

申请号：EP08866597

申请日：2008-12-22

Applicant: IBM

Inventor： BASKER VEERARAGHAVAN S ,  PARUCHURI VAMSI ,  COTTE JOHN M ,  FURUKAWA TOSHIHARU ,  TONTI WILLIAM ,  DELIGIANNI HARIKLIA

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L29/517 ,  H01L29/66545

公开(公告)号：EP1668696A4

公开(公告)日：2008-09-03

申请号：EP04783206

申请日：2004-09-07

Applicant: IBM

Inventor： CHOU ANTHONY I ,  FURUKAWA TOSHIHARU ,  VAREKAMP PATRICK R ,  SLEIGHT JEFFREY W ,  SEKIGUCHI AKIHISA

IPC: H01L21/8238

CPC classification number: H01L21/28202 ,  H01L21/823842 ,  H01L21/823857

Abstract: A method of forming CMOS semiconductor (10) materials with PFET (16) and NFET (14) areas formed on a semiconductor substrate (12), covered respectively with a PFET (16) and NFET (14) gate dielectric layers composed of silicon oxide and different degrees of nitridation (18D and 18E) thereof. Provide a silicon substrate (12) with a PFET (16) area and an NFET (14) area and form PFET and NFET gate oxide layers thereover. Provide nitridation of the PFET gate oxide layer above the PFET area to form the PFET gate dielectric layer (42) above the PFET area with a first concentration level of nitrogen atoms in the PFET gate dielectric I ayer above the PFET area. Provide nitridation of the NFET gate oxide layer to form the NFET gate dielectric layer (40) above the NFET area with a different concentration level of nitrogen atoms from the first concentration level. The NFET gate dielectric layer (40) and the PFET gate dielectric layer (42) can have the same thickness.

公开(公告)号：EP1436843A4

公开(公告)日：2008-11-26

申请号：EP02780350

申请日：2002-09-17

Applicant: IBM

Inventor： PARK BYEONGJU ,  FURUKAWA TOSHIHARU ,  MANDELMAN JACK

IPC: H01L29/41 ,  H01L29/76 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78618

Abstract: The present invention relates to a wrapped-gate transistor including a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions (28) are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer (40) is formed on the substrate. A gate electrode (42) is formed on the gate dielectric layer (40) to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric (40) therebetween. The substrate is a silicon island (12) formed on an insulation layer of an SOI (silicon-on-insulator) substrate or a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions (28) are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces. The wrapped-gate structure provides a better and quicker potential control within the channel area, which yields steep sub-threshold slope and low sensitivity to the 'body-to-source' voltage.

公开(公告)号：EP1849187A4

公开(公告)日：2010-11-17

申请号：EP06717977

申请日：2006-01-10

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76885 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76874 ,  H01L23/5283 ,  H01L23/53209 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

公开(公告)号：EP1430536A4

公开(公告)日：2006-04-26

申请号：EP02796462

申请日：2002-08-29

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  LEAS JAMES M ,  MA WILLIAM H L ,  RABIDOUX PAUL A

IPC: H01L21/336 ,  H01L21/60 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8238 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L29/78642 ,  H01L21/2255 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

Abstract: A vertical transistor particularly suitable for high density integration includes potentially independent gate structures (3230) o opposite sides of a semiconductor pillar (2910) formed by etching in a trench. The gate structure is surrounded by insulting material (2620) which is selectively etchable to isolation material surrounding the transistor. A contact (3820) is made to the lower end of the pillar by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap (2730) and sidewalls of selectively etchable materials so that gate and source connection openings (3720, 3620) can also be made by selective etching with good registration tolerance.