公开(公告)号：EP2522027A4

公开(公告)日：2014-05-28

申请号：EP11732060

申请日：2011-01-05

Applicant: IBM

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  LIN CHUNG HSUN ,  SLEIGHT JEFFREY W

IPC: H01L21/336 ,  H01L21/265 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/78612 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/42384 ,  H01L29/66772

Abstract: In one exemplary embodiment of the invention, an asymmetric P-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric P-type field effect transistor is operable to act as a symmetric P-type field effect transistor.

公开(公告)号：EP2801105A4

公开(公告)日：2014-12-03

申请号：EP12864109

申请日：2012-12-13

Applicant: IBM

Inventor： BANGSARUNTIP SARUNYA ,  COHEN GUY ,  MAJUMDAR AMLAN ,  SLEIGHT JEFFREY W

IPC: H01L21/336 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

公开(公告)号：EP2394304A4

公开(公告)日：2014-05-21

申请号：EP10739003

申请日：2010-02-02

Applicant: IBM

Inventor： BANGSARUNTIP SARUNYA ,  COHEN GUY ,  SLEIGHT JEFFREY W

IPC: H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02667 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696 ,  Y10S977/762

公开(公告)号：EP2011208A4

公开(公告)日：2011-09-28

申请号：EP07759794

申请日：2007-03-30

Applicant: IBM

Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

IPC: H02H9/00 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

公开(公告)号：EP1668696A4

公开(公告)日：2008-09-03

申请号：EP04783206

申请日：2004-09-07

Applicant: IBM

Inventor： CHOU ANTHONY I ,  FURUKAWA TOSHIHARU ,  VAREKAMP PATRICK R ,  SLEIGHT JEFFREY W ,  SEKIGUCHI AKIHISA

IPC: H01L21/8238

CPC classification number: H01L21/28202 ,  H01L21/823842 ,  H01L21/823857

Abstract: A method of forming CMOS semiconductor (10) materials with PFET (16) and NFET (14) areas formed on a semiconductor substrate (12), covered respectively with a PFET (16) and NFET (14) gate dielectric layers composed of silicon oxide and different degrees of nitridation (18D and 18E) thereof. Provide a silicon substrate (12) with a PFET (16) area and an NFET (14) area and form PFET and NFET gate oxide layers thereover. Provide nitridation of the PFET gate oxide layer above the PFET area to form the PFET gate dielectric layer (42) above the PFET area with a first concentration level of nitrogen atoms in the PFET gate dielectric I ayer above the PFET area. Provide nitridation of the NFET gate oxide layer to form the NFET gate dielectric layer (40) above the NFET area with a different concentration level of nitrogen atoms from the first concentration level. The NFET gate dielectric layer (40) and the PFET gate dielectric layer (42) can have the same thickness.

公开(公告)号：EP2522032A4

公开(公告)日：2014-05-28

申请号：EP11732064

申请日：2011-01-05

Applicant: IBM

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  LIN CHUNG-HSUN ,  SLEIGHT JEFFREY W

IPC: H01L29/786 ,  H01L21/265 ,  H01L21/336 ,  H01L29/66

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/42384 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78615

Abstract: In one exemplary embodiment of the invention, an asymmetric N-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric N-type field effect transistor is operable to act as a symmetric N-type field effect transistor.

公开(公告)号：EP2396812A4

公开(公告)日：2012-08-01

申请号：EP10767544

申请日：2010-04-15

Applicant: IBM

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  MO RENEE T ,  NARAYANAN VIJAY ,  SLEIGHT JEFFREY W

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7856 ,  H01L29/66795

公开(公告)号：EP1875507A4

公开(公告)日：2009-08-05

申请号：EP06740000

申请日：2006-03-30

Applicant: IBM

Inventor： BERNSTEIN KERRY ,  SLEIGHT JEFFREY W ,  YANG MIN

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/1207

Abstract: The present invention provides a semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of circuits built from the combination of the SOI and bulk-Si region FETs.

公开(公告)号：EP1875516A4

公开(公告)日：2008-08-13

申请号：EP06739771

申请日：2006-03-27

Applicant: IBM

Inventor： CHANG LELAND ,  NARASIMHA SHREESH ,  ROHRER NORMAN J ,  SLEIGHT JEFFREY W

IPC: H01L21/8244 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L27/1207

Abstract: The present invention provides a 6T-SRAM semiconductintg structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk Si-region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has a silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.

Abstract translation: 本发明提供了一种6T-SRAM半导体结构，其包括具有SOI区和体硅区的衬底，其中SOI区和体硅区具有相同或不同的结晶取向; 隔离SOI区域与体硅区域的隔离区域; 以及位于所述SOI区域中的至少一个第一器件和位于所述体硅区域中的至少一个第二器件。 SOI区域在绝缘层顶上具有硅层。 体硅区还包括位于第二器件下方的阱区和与阱区的接触，其中接触稳定了浮体效应。 阱接触也用于控制体硅区域中的FET的阈值电压，以优化由SOI和体硅区域FET的组合构建的SRAM单元的功率和性能。