Patent search ap:("IBM") AND inv:"GOUSEV EVGENI P" Page 1

1.

发明公开
SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH K DIELECTRICS 有权
Title translation: 层层壁垒的选择性实施旨在实现阈值电压控制在CMOS元件具有高K电介质的生产

公开(公告)号：EP1766691A4

公开(公告)日：2011-06-29

申请号：EP05732384

申请日：2005-03-30

Applicant: IBM

Inventor： BOJARCZUK NESTOR A JR , CABRAL CYRIL JR , CARTIER EDUARD A , COPEL MATTHEW W , FRANK MARTIN M , GOUSEV EVGENI P , GUHA SUPRATIK , JAMMY RAJARAO , NARAYANAN VIJAY , PARUCHURI VAMSI K

IPC: H01L31/113 , H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L31/119

CPC classification number: H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517

2.

发明公开
LOW THRESHOLD VOLTAGE SEMICONDUCTOR DEVICE WITH DUAL THRESHOLD VOLTAGE CONTROL MEANS 审中-公开
Title translation: 用双阈值电压控制装置低阈值电压半导体部件

公开(公告)号：EP1949447A4

公开(公告)日：2009-11-11

申请号：EP06825854

申请日：2006-10-12

Applicant: IBM

Inventor： CARTER EDUARD A , COPEL MATTHEW W , FRANK MARTIN M , GOUSEV EVGENI P , JAMISON PAUL C , JAMMY RAJARAO , LINDER BARRY P , NARAYANAN VIJAY

IPC: H01L29/51 , H01L21/28 , H01L29/10 , H01L29/78

CPC classification number: H01L29/513 , H01L21/28194 , H01L21/28238 , H01L21/823807 , H01L29/105 , H01L29/1083 , H01L29/517 , H01L29/518 , H01L29/6659 , H01L29/7833

3.

发明公开
NITROGEN-CONTAINING FIELD EFFECT TRANSISTOR GATE STACK CONTAINING A THRESHOLD VOLTAGE CONTROL LAYER FORMED VIA DEPOSITION OF A METAL OXIDE 审中-公开
Title translation: WITH A形成的金属氧化物阈值电压控制层的矿床氮场效应晶体管栅极堆栈

公开(公告)号：EP1825521A4

公开(公告)日：2008-10-01

申请号：EP05820881

申请日：2005-11-01

Applicant: IBM

Inventor： BOJARCZUK NESTOR A JR , CABRAL CYRIL JR , CARTIER EDUARD A , FRANK MARTIN M , GOUSEV EVGENI P , GUHA SUPRATIK , JAMISON PAUL C , JAMMY RAJARAO , NARAYANAN VIJAY , PARUCHURI VAMSI K

IPC: H01L29/792 , H01L21/336 , H01L29/76 , H01L29/94 , H01L31/00

CPC classification number: H01L29/513 , H01L21/28194 , H01L21/2822 , H01L21/823828 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517 , H01L29/518

Abstract: A semiconductor structure is provided that includes a V t stabilization layer between a gate dielectric and a gate electrode. The V t stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the provision that when the V t stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

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