Patent search ap:("IBM") AND inv:"PARUCHURI VAMSI K" Page 1

1.

发明公开
INTRODUCTION OF METAL IMPURITY TO CHANGE WORKFUNCTION OF CONDUCTIVE ELECTRODES 审中-公开
Title translation: 引言金属杂质修订工作职能引出电极

公开(公告)号：EP1974372A4

公开(公告)日：2009-12-09

申请号：EP07716303

申请日：2007-01-03

Applicant: IBM

Inventor： CHUDZIK MICHAEL P , DORIS BRUCE B , GUHA SUPRATIK , JAMMY RAJARAO , NARAYANAN VIJAY , PARUCHURI VAMSI K , WANG YUN Y , KWONG HON WONG KEITH

IPC: H01L21/336 , H01L21/28 , H01L29/49 , H01L29/51

CPC classification number: H01L29/517 , H01L21/28088 , H01L21/823828 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/78 , H01L2924/0002 , H01L2924/00

2.

发明公开
SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH K DIELECTRICS 有权
Title translation: 层层壁垒的选择性实施旨在实现阈值电压控制在CMOS元件具有高K电介质的生产

公开(公告)号：EP1766691A4

公开(公告)日：2011-06-29

申请号：EP05732384

申请日：2005-03-30

Applicant: IBM

Inventor： BOJARCZUK NESTOR A JR , CABRAL CYRIL JR , CARTIER EDUARD A , COPEL MATTHEW W , FRANK MARTIN M , GOUSEV EVGENI P , GUHA SUPRATIK , JAMMY RAJARAO , NARAYANAN VIJAY , PARUCHURI VAMSI K

IPC: H01L31/113 , H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L31/119

CPC classification number: H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517

3.

发明公开
NITROGEN-CONTAINING FIELD EFFECT TRANSISTOR GATE STACK CONTAINING A THRESHOLD VOLTAGE CONTROL LAYER FORMED VIA DEPOSITION OF A METAL OXIDE 审中-公开
Title translation: WITH A形成的金属氧化物阈值电压控制层的矿床氮场效应晶体管栅极堆栈

公开(公告)号：EP1825521A4

公开(公告)日：2008-10-01

申请号：EP05820881

申请日：2005-11-01

Applicant: IBM

Inventor： BOJARCZUK NESTOR A JR , CABRAL CYRIL JR , CARTIER EDUARD A , FRANK MARTIN M , GOUSEV EVGENI P , GUHA SUPRATIK , JAMISON PAUL C , JAMMY RAJARAO , NARAYANAN VIJAY , PARUCHURI VAMSI K

IPC: H01L29/792 , H01L21/336 , H01L29/76 , H01L29/94 , H01L31/00

CPC classification number: H01L29/513 , H01L21/28194 , H01L21/2822 , H01L21/823828 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517 , H01L29/518

Abstract: A semiconductor structure is provided that includes a V t stabilization layer between a gate dielectric and a gate electrode. The V t stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the provision that when the V t stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

4.

发明公开
USING METAL/METAL NITRIDE BILAYERS AS GATE ELECTRODES IN SELF-ALIGNED AGGRESSIVELY SCALED CMOS DEVICES 有权
Title translation: 金属/金属氮化物双层AS栅极电极的自对准AGGRESSIVE缩放CMOS组件使用

公开(公告)号：EP1872407A4

公开(公告)日：2011-09-14

申请号：EP06750529

申请日：2006-04-18

Applicant: IBM

Inventor： CARTIER EDUARD A , COPEL MATTHEW W , DORIS BRUCE B , JAMMY RAJARAO , KIM YOUNG-HEE , LINDER BARRY P , NARAYANAN VIJAY , PARUCHURI VAMSI K , WONG KEITH KWONG HON

IPC: H01L21/84 , H01L21/8238 , H01L27/092

CPC classification number: H01L21/823842

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