公开(公告)号：EP2292072A4

公开(公告)日：2016-12-28

申请号：EP09770750

申请日：2009-06-12

申请人： INTEL CORP

发明人： GINZBURG BORIS ,  BEN-PORATH SHARON ,  KAIDAR OREN ,  AVITAL SHLOMO ,  SHARAGA AVISHAY ,  FUDIM MAX ,  FRIEDLANDER ERAN

IPC分类号： H04W88/06 ,  H04B1/40

CPC分类号： H04W88/06 ,  H04W52/0274 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/146

摘要： An embodiment of the present invention provides an apparatus, comprising a network adapter configured for wireless communication using more than one technology using distributed management and wherein the network adapter is configured to share a plurality of shared hardware components by automatically turning all other comms to OFF when one comm is turned to ON.

摘要翻译： 本发明的实施例提供有关装置，包括被配置为使用多于一种技术使用分布式管理和worin网络适配器的无线通信的网络适配器被配置为通过所有其他通讯科自动转向OFF当共享共享硬件组件的多元性 一个COMM转至ON。

公开(公告)号：EP2684123A4

公开(公告)日：2014-12-31

申请号：EP11861151

申请日：2011-12-29

申请人： INTEL CORP

发明人： GINZBURG BORIS ,  NATANZON ESFIR ,  OSADCHIY ILYA ,  RONEN RONNY ,  WEISSMANN ELIEZER ,  ZACH YOAV ,  FARRELL ROBERT L

IPC分类号： G06F12/10 ,  G06F9/06 ,  G06F9/30 ,  G06F12/08 ,  G06F13/14

CPC分类号： G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/302 ,  G06F2212/682

摘要： Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.

摘要翻译： 页面错误在图形处理单元所产生可通过对操作系统运行的中央处理单元上进行处理。 在一些实施方案中，本bedeutet，DASS取消固定存储器可用于图形处理单元。 在图形处理单元，使用未固定的存储器可扩展图形处理单元的在某些情况下的功能。

公开(公告)号：EP2798477A4

公开(公告)日：2015-08-26

申请号：EP11878938

申请日：2011-12-29

申请人： INTEL CORP

发明人： RONEN RONNY ,  OSADCHIY ILYA ,  GINZBURG BORIS

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F11/07 ,  G06F12/08 ,  G06F13/00

CPC分类号： G06F11/0784 ,  G06F9/30036 ,  G06F9/30043 ,  G06F12/08

摘要： A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

公开(公告)号：EP2726978A4

公开(公告)日：2014-12-17

申请号：EP12807063

申请日：2012-06-29

申请人： INTEL CORP

发明人： SHEAFFER GAD ,  GINZBURG BORIS ,  RONEN RONNY ,  WEISSMANN ELIEZER

IPC分类号： G06F9/06 ,  G06F12/08 ,  G06F12/10 ,  G06F12/12

CPC分类号： G06F12/1027 ,  G06F12/0804 ,  G06F12/126 ,  G06F13/1663 ,  G06F2212/303 ,  G06F2212/657 ,  G06F2212/684

摘要： A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device (e.g., a graphics processing unit, GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. In one embodiment, the device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs.

公开(公告)号：EP2831721A4

公开(公告)日：2016-01-13

申请号：EP12873375

申请日：2012-03-30

申请人： INTEL CORP

发明人： RONEN RONNY ,  WEISSMANN ELIEZER ,  GINZBURG BORIS ,  VAITHIANATHAN KARTHIKEYAN KARTHIK ,  COHEN EHUD

IPC分类号： G06F9/06 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F12/10 ,  G06F15/80

CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/461 ,  G06F9/485

摘要： An apparatus is described having multiple cores, each core having: a) an accelerator; and, b) a general purpose CPU coupled to the accelerator. The general purpose CPU has functional unit logic circuitry to execute an instruction that returns an amount of storage space to store context information of the accelerator.

公开(公告)号：EP2098024A4

公开(公告)日：2013-09-04

申请号：EP07862380

申请日：2007-11-29

申请人： INTEL CORP

发明人： QI EMILY H ,  FUDIM MAX ,  MACIOCCO CHRISTIAN ,  HATTIG MYRON ,  GINZBURG BORIS

IPC分类号： H04W36/02 ,  H04W84/12

CPC分类号： H04W36/02 ,  H04W84/12

公开(公告)号：EP2831750A4

公开(公告)日：2016-05-11

申请号：EP12873133

申请日：2012-03-30

申请人： INTEL CORP

发明人： RONEN RONNY ,  GINZBURG BORIS ,  WEISSMANN ELIEZER

IPC分类号： G06F15/78 ,  G06F9/38 ,  G06F9/48 ,  G06F12/10

CPC分类号： G06F9/4881 ,  G06F9/38 ,  G06F9/3877 ,  G06F12/10 ,  G06F12/1027 ,  G06F15/7807 ,  G06F2212/301

摘要： An apparatus is described having multiple cores, each core having: a) a CPU; b) an accelerator; and, c) a controller and a plurality of order buffers coupled between the CPU and the accelerator. Each of the order buffers is dedicated to a different one of the CPU's threads. Each one of the order buffers is to hold one or more requests issued to the accelerator from its corresponding thread. The controller is to control issuance of the order buffers' respective requests to the accelerator.

公开(公告)号：EP2831693A4

公开(公告)日：2015-10-21

申请号：EP12873212

申请日：2012-03-30

申请人： INTEL CORP

发明人： WEISSMANN ELIEZER ,  VAITHIANATHAN KARTHIKEYAN KARTHIK ,  ZACH YOAV ,  GINZBURG BORIS ,  RONEN RONNY

IPC分类号： G06F1/00 ,  G06F9/06 ,  G06F9/38 ,  G06F12/10 ,  G06F13/14

CPC分类号： G06F12/0811 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：EP2737396A4

公开(公告)日：2015-06-10

申请号：EP12819390

申请日：2012-06-29

申请人： INTEL CORP

发明人： GINZBURG BORIS ,  NATANZON ESFIRUSH ,  OSADCHIY ILYA ,  ZACH YOAV

IPC分类号： G06F9/06 ,  G06F15/163

CPC分类号： G06T1/20 ,  G06T1/60

摘要： A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

公开(公告)号：EP2686765A4

公开(公告)日：2014-12-31

申请号：EP11861225

申请日：2011-12-29

申请人： INTEL CORP

发明人： GINZBURG BORIS ,  NATANZON ESFIRUSH ,  OSADCHIY ILYA ,  RONEN RONNY ,  WEISSMANN ELIEZER ,  ZACH YOAV ,  FARRELL ROBERT L

IPC分类号： G06F9/06 ,  G06F9/22 ,  G06F11/07 ,  G06F12/08

CPC分类号： G06F12/08 ,  G06F2212/302

摘要： Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.