-
公开(公告)号：EP2788979A4
公开(公告)日：2015-07-22
申请号：EP11876968
申请日：2011-12-06
申请人： INTEL CORP
发明人： RAYCHOWDHURY ARIJIT , BELTMAN WILLEM M , TSCHANZ JAMES W , TOKUNAGA CARLOS , DEISHER MICHAEL E , WALSH THOMAS E
CPC分类号： G10L15/20 , G06F1/3234 , G06F17/142 , G10L15/22 , G10L15/285 , G10L21/0208 , G10L21/0232 , G10L25/18 , G10L25/84 , G10L2015/223 , G10L2021/02087
摘要： Methods of enabling voice processing with minimal power consumption includes recording time-domain audio signal at a first clock frequency and a first voltage, and performing Fast Fourier Transform (FFT) operations on the time-domain audio signal at a second clock frequency to generate frequency-domain audio signal. The frequency domain audio signal may be enhanced to obtain better signal to noise ratio, through one or multiple filtering and enhancing techniques. The enhanced audio signal may be used to generate the total signal energy and estimate the background noise energy. Decision logic may determine from the signal energy and the background noise, the presence or absence of the human voice. The first clock frequency may be different from the second clock frequency.
-
公开(公告)号：EP3084916A4
公开(公告)日：2018-01-17
申请号：EP13899423
申请日：2013-12-20
申请人： INTEL CORP
CPC分类号： H02M3/073 , G06F3/041 , H02J7/00 , H03K3/0377 , H03K19/21
摘要： Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.
-
3.发明公开RESILIENT REGISTER FILE CIRCUIT FOR DYNAMIC VARIATION TOLERANCE AND METHOD OF OPERATING THE SAME 审中-公开灵活的注册机器人VERIISCHECHERSCHALTUNGFÜRDYNAMISCHE VARIATION STOLERANZ UND BETRIEBSVERFAHRENDAFÜR
公开(公告)号：EP2798640A4
公开(公告)日：2016-10-05
申请号：EP11879150
申请日：2011-12-28
申请人： INTEL CORP
CPC分类号： G06F11/1068 , G06F9/30141 , G06F9/3861 , G06F11/0751 , G06F11/1008 , G11C7/18 , G11C29/42 , G11C29/52
摘要： The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.
摘要翻译： 所公开的系统和方法检测并校正由于减少或消除CPU的电源电压保护带和/或频率保护带而可能发生的寄存器文件读取路径错误，从而提高系统的总体能量效率。
-
公开(公告)号：EP2901235A4
公开(公告)日：2016-09-28
申请号：EP12885472
申请日：2012-09-25
申请人： INTEL CORP
IPC分类号： G05F1/56
摘要： Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference.
摘要翻译： 描述了一种装置，包括：第一振荡器，用于产生第一时钟信号第二振荡器以产生第二时钟信号; 相位频率检测器，用于检测第一和第二时钟信号之间的相位差，并产生相位差; 以及耦合到负载的输出级，以根据相位差产生用于负载的电源。
-
公开(公告)号：EP3286761A1
公开(公告)日：2018-02-28
申请号：EP16783534
申请日：2016-02-19
申请人： INTEL CORP
CPC分类号： G11C11/1659 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.
-
公开(公告)号：EP3114690A4
公开(公告)日：2017-10-18
申请号：EP14884884
申请日：2014-03-07
申请人： INTEL CORP
CPC分类号： G11C11/1695 , G06F21/34 , G06F21/73 , G06F21/79 , G09C1/00 , G11C7/16 , G11C7/24 , G11C11/16 , G11C11/1659 , G11C11/1673 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C13/0059 , G11C2013/0045 , G11C2013/005 , H03M1/12 , H03M1/124 , H04L9/0866
摘要： Described is a physically unclonable functional circuit comprising: a resistive memory device (e.g., an MTJ device) having at least two terminals; a transistor coupled to one of the at least two terminals of the resistive memory device; and an analog-to-digital converter (ADC) having an input coupled to the one of the at least two terminals of the resistive memory device.
-
公开(公告)号：EP2791753A4
公开(公告)日：2015-07-29
申请号：EP11877465
申请日：2011-12-14
申请人： INTEL CORP
CPC分类号： H03K19/017509 , G06F1/10 , G06F1/3296 , Y02D10/172
摘要： Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.009 秒)
