公开(公告)号：EP3055809A4

公开(公告)日：2017-05-31

申请号：EP14852401

申请日：2014-09-25

Applicant: INTEL CORP

Inventor： GULLEY SEAN M ,  GOPAL VINODH ,  FEGHALI WAJDI K ,  GUILFORD JAMES D ,  WOLRICH GILBERT M ,  YAP KIRK S

IPC: H04L9/06 ,  H04L9/32

CPC classification number: H04L9/0643 ,  G06F21/72 ,  H04L9/3242 ,  H04L2209/12 ,  H04L2209/125 ,  H04L2209/20

Abstract: One embodiment provides an apparatus. The apparatus includes a single instruction multiple data (SIMD) hash module configured to apportion at least a first portion of a message of length L to a number (S) of segments, the message including a plurality of sequences of data elements, each sequence including S data elements, a respective data element in each sequence apportioned to a respective segment, each segment including a number N of blocks of data elements and to hash the S segments in parallel, resulting in S segment digests, the S hash digests based, at least in part, on an initial value and to store the S hash digests; a padding module configured to pad a remainder, the remainder corresponding to a second portion of the message, the second portion related to the length L of the message, the number of segments and a block size; and a non-SIMD hash module configured to hash the padded remainder, resulting in an additional hash digest and to store the additional hash digest.

Abstract translation: 一个实施例提供一种装置。 该装置包括被配置为将长度为L的消息的至少第一部分分配给段（S）的单指令多数据（SIMD）散列模块，该消息包括多个数据元素序列，每个序列包括 S数据元素，每个序列中的相应数据元素被分配到相应的段，每个段包括N个数据元素块并且并行地散列S个段，导致S段摘要，S散列摘要基于 至少部分取决于初始值并存储S散列摘要; 填充模块，被配置为填充剩余部分，其余部分对应于所述消息的第二部分，所述第二部分与所述消息的长度L有关，所述片段的数量和块大小; 以及非SIMD散列模块，其被配置为对填充后的余数进行散列，从而产生附加的散列摘要并存储附加的散列摘要。

公开(公告)号：EP2872987A4

公开(公告)日：2016-02-24

申请号：EP13816262

申请日：2013-07-10

Applicant: INTEL CORP

Inventor： GULLEY SEAN M ,  FEGHALI WAJDI K ,  GOPAL VINODH ,  GUILFORD JAMES D ,  WOLRICH GILBERT M ,  YAP KIRK S

IPC: H04L9/32 ,  G06F5/06 ,  G06F21/64 ,  H04L9/06

CPC classification number: G06F5/06 ,  G06F21/64 ,  H04L9/0643 ,  H04L9/3236 ,  H04L2209/12 ,  H04L2209/20

Abstract: Technologies for executing a serial data processing algorithm on a single variable length data buffer includes streaming segments of the buffer into a data register, executing the algorithm on each of the segments in parallel, and combining the results of executing the algorithm on each of the segments to form the output of the serial data processing algorithm.

公开(公告)号：EP2872990A4

公开(公告)日：2016-03-02

申请号：EP13816809

申请日：2013-07-10

Applicant: INTEL CORP

Inventor： GULLEY SEAN M ,  FEGHALI WAJDI K ,  GOPAL VINODH ,  GUILFORD JAMES D ,  WOLRICH GILBERT M ,  YAP KIRK S

IPC: H04L9/32 ,  G06F5/06 ,  G06F21/64 ,  H04L9/06

CPC classification number: G06F5/06 ,  G06F21/64 ,  H04L9/0643 ,  H04L9/3236 ,  H04L2209/12 ,  H04L2209/20

Abstract: Technologies for executing a serial data processing algorithm on a single variable length data buffer includes streaming segments of the buffer into a data register, executing the algorithm on each of the segments in parallel, and combining the results of executing the algorithm on each of the segments to form the output of the serial data processing algorithm.

公开(公告)号：EP2832036A4

公开(公告)日：2015-11-25

申请号：EP12873156

申请日：2012-03-30

Applicant: INTEL CORP

Inventor： YAP KIRK S ,  WOLRICH GILBERT M ,  GUILFORD JAMES D ,  GOPAL VINODH ,  OZTURK ERDINC ,  GULLEY SEAN M ,  FEGHALI WAJDI K ,  DIXON MARTIN G

IPC: H04L9/32 ,  G06F9/30 ,  H04L9/06

CPC classification number: G06F9/3016 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/384 ,  G06F9/3895 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F15/8007 ,  G06F21/602 ,  G06F2212/452 ,  G06F2212/68 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/125

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.