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    PARALLEL DIRECTION DECODE CIRCUITS FOR NETWORK-ON-CHIP
    3.
    发明公开
    PARALLEL DIRECTION DECODE CIRCUITS FOR NETWORK-ON-CHIP 审中-公开
    网络芯片上的并行方向解码电路

    公开(公告)号：EP3235194A1

    公开(公告)日：2017-10-25

    申请号：EP15870589.7

    申请日：2015-11-19

    申请人： INTEL Corporation

    发明人： ANDERS, Mark A. ,  CHEN, Gregory K. ,  KAUL, Himanshu

    IPC分类号： H04L12/771 ,  H04L12/931 ,  G06F13/14

    CPC分类号： H04L45/72 ,  H04L45/16 ,  H04L45/60 ,  H04L47/33 ,  H04L49/109 ,  H04L49/25

    摘要： A first packet and a first direction associated with the first packet are received. The first packet is forwarded to an output port of a plurality of output ports of the first router based on the first direction associated with the first packet. A second direction associated with the first packet is determined. The second direction is based at least on an address of the first packet. The first packet and the second direction are forwarded through the output port of the first router to a second router.

    摘要翻译： 接收与第一分组相关联的第一分组和第一方向。 基于与第一分组相关联的第一方向将第一分组转发到第一路由器的多个输出端口中的输出端口。 确定与第一分组相关联的第二方向。 第二方向至少基于第一分组的地址。 第一包和第二方向通过第一路由器的输出端口转发到第二路由器。

    EVENT DRIVEN AND TIME HOPPING NEURAL NETWORK
    7.
    发明公开
    EVENT DRIVEN AND TIME HOPPING NEURAL NETWORK 审中-公开

    公开(公告)号：EP3343459A1

    公开(公告)日：2018-07-04

    申请号：EP17205510.5

    申请日：2017-12-05

    申请人： Intel Corporation

    发明人： SENGUPTA, Abhronil ,  CHEN, Gregory K. ,  KUMAR, Raghavan ,  SUMBUL, Huseyin Ekin ,  KNAG, Phil

    IPC分类号： G06N3/04

    CPC分类号： G06N3/08 ,  G06N3/049

    摘要： In one embodiment, a processor is to store a membrane potential of a neural unit of a neural network; and calculate, at a particular time-step of the neural network, a change to the membrane potential of the neural unit occurring over multiple time-steps that have elapsed since the last time-step at which the membrane potential was updated, wherein each of the multiple time-steps that have elapsed since the last time-step is associated with at least one input to the neural unit that affects the membrane potential of the neural unit.

    COMBINED GUARANTEED THROUGHPUT AND BEST EFFORT NETWORK-ON-CHIP
    8.
    发明公开
    COMBINED GUARANTEED THROUGHPUT AND BEST EFFORT NETWORK-ON-CHIP 审中-公开
    组合保证吞吐量和最佳效果网络芯片

    公开(公告)号：EP3238390A1

    公开(公告)日：2017-11-01

    申请号：EP15873990.4

    申请日：2015-11-24

    申请人： INTEL Corporation

    发明人： CHEN, Gregory K. ,  ANDERS, Mark A. ,  KAUL, Himanshu ,  KRISHNAMURTHY, Ram K. ,  STILLMAKER, Aaron T.

    IPC分类号： H04L12/771 ,  H04L12/931 ,  G06F13/14

    CPC分类号： H04L47/625 ,  G06F15/7825 ,  H04L12/6402 ,  H04L47/72 ,  H04L49/30

    摘要： A first packet-switched reservation request is received. Data associated with the first packet-switched reservation request is communicated through a first circuit-switched channel according to a best effort communication scheme. A second packet-switched reservation request is received. Data associated with the second packet-switched reservation request is communicated through a second circuit-switched channel according to a guaranteed throughput communication scheme.

    摘要翻译： 接收到第一分组交换预约请求。 根据尽力而为通信方案通过第一电路交换信道传送与第一分组交换预留请求相关联的数据。 接收到第二分组交换预留请求。 根据保证的吞吐量通信方案通过第二电路交换信道传送与第二分组交换预留请求相关联的数据。

    EDGE-AWARE SYNCHRONIZATION OF A DATA SIGNAL
    9.
    发明公开
    EDGE-AWARE SYNCHRONIZATION OF A DATA SIGNAL 审中-公开
    数据信号的边缘意识同步

    公开(公告)号：EP3230818A1

    公开(公告)日：2017-10-18

    申请号：EP15867374.9

    申请日：2015-11-11

    申请人： Intel Corporation

    发明人： CHEN, Gregory K. ,  ANDERS, Mark A. ,  KAUL, Himanshu

    IPC分类号： G06F1/12

    CPC分类号： H03K5/135 ,  G06F5/10 ,  G11C8/18 ,  G11C19/287 ,  H03K2005/00013

    摘要： A signal comprising a first edge and a second edge is received. The first edge of the signal is synchronized with a first clock and the synchronized first edge of the signal is passed to an output. The synchronization results in a delay of the first edge of the signal. The second edge of the signal is passed to the output. The passed second edge of the signal has a delay that is less than the delay of the first edge of the signal by at least one clock cycle of the first clock.

    摘要翻译： 接收包括第一边缘和第二边缘的信号。 信号的第一个边沿与第一个时钟同步，信号的同步的第一个边沿传送到输出。 同步会导致信号的第一个边沿延迟。 信号的第二个边沿被传递到输出端。 信号的第二个边沿的延迟小于第一个时钟周期的至少一个信号的第一个边沿的延迟。