公开(公告)号：EP3382556A1

公开(公告)日：2018-10-03

申请号：EP18165216.5

申请日：2011-09-30

申请人： INTEL Corporation

发明人： Nale, Bill ,  RAMANUJAN, Raj K. ,  SWAMINATHAN, Muthukumar P. ,  THOMAS, Tessil ,  POLEPEDDI, Taarinya

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F11/10 ,  G06F13/14 ,  G06F13/16 ,  G06F9/46 ,  G06F13/42 ,  G06F13/36 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0811 ,  G06F13/40

CPC分类号： G06F13/1694 ,  G06F9/467 ,  G06F11/1064 ,  G06F12/0238 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0897 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/42 ,  G06F13/4234 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/2024 ,  G06F2212/7203 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.