公开(公告)号：EP3602633A1

公开(公告)日：2020-02-05

申请号：EP17903860.9

申请日：2017-03-31

Applicant: INTEL Corporation

Inventor： LE, Van, H. ,  SHARMA, Abhishek, A. ,  PILLARISETTY, Ravi ,  DEWEY, Gilbert, W. ,  SHIVARAMAN, Shriram ,  TRONIC, Tristan, A. ,  GARDNER, Sanaz ,  GHANI, Tahir

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/108

公开(公告)号：EP3588579A1

公开(公告)日：2020-01-01

申请号：EP19191370.6

申请日：2011-12-07

Applicant: INTEL Corporation

Inventor： MURTHY, Anand S. ,  GLASS, Glenn A. ,  GHANI, Tahir ,  PILLARISETTY, Ravi ,  MUKHERJEE, Niloy ,  KAVALIEROS, Jack T. ,  KOTLYAR, Roza ,  RACHMADY, Willy ,  LIU, Mark Y.

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/285 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/167 ,  H01L29/165

Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm -3 . A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

公开(公告)号：EP3516699A1

公开(公告)日：2019-07-31

申请号：EP16916984.4

申请日：2016-09-24

Applicant: INTEL Corporation

Inventor： GEORGE, Hubert C. ,  PILLARISETTY, Ravi ,  ROBERTS, Jeanette M. ,  THOMAS, Nicole K. ,  CLARKE, James S.

IPC: H01L29/775 ,  H01L29/12 ,  H01L29/786 ,  H01L29/66

公开(公告)号：EP2705537B1

公开(公告)日：2018-07-25

申请号：EP11864827.8

申请日：2011-12-22

Applicant: Intel Corporation

Inventor： PILLARISETTY, Ravi

IPC: H01L29/739 ,  H01L29/78 ,  H01L21/336 ,  H01L29/66

CPC classification number: H01L29/4175 ,  H01L21/28581 ,  H01L21/32051 ,  H01L29/1029 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7391 ,  H01L29/772 ,  H01L29/7783

Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.

公开(公告)号：EP3329515A1

公开(公告)日：2018-06-06

申请号：EP15900522.2

申请日：2015-07-31

Applicant: Intel Corporation

Inventor： KARPOV, Elijah V. ,  MAJHI, Prashant ,  KOTLYAR, Roza ,  MUKHERJEE, Niloy ,  KUO, Charles C. ,  SHAH, Uday ,  PILLARISETTY, Ravi ,  CHAU, Robert S.

IPC: H01L29/02

CPC classification number: H01L29/7869 ,  H01L27/0705 ,  H01L27/1225 ,  H01L29/02 ,  H01L29/4908 ,  H01L29/78603 ,  H01L29/78642

Abstract: A microelectronic device having a functional metal oxide channel may be fabricated on a microelectronic substrate that can be utilized in very large scale integration, such as a silicon substrate, by forming a buffer transition layer between the microelectronic substrate and the functional metal oxide channel. In one embodiment, the microelectronic device may be a microelectronic transistor with a source structure and a drain structure formed on the buffer transition layer, wherein the source structure and the drain structure abut opposing sides of the functional metal oxide channel and a gate dielectric is disposed between a gate electrode and the functional metal oxide channel. In another embodiment, the microelectronic device may be a two-terminal microelectronic device.

公开(公告)号：EP3235008A1

公开(公告)日：2017-10-25

申请号：EP14908580.5

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： DASGUPTA, Sansaptak ,  THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  GARDNER, Sanaz K. ,  SUNG, Seung Hoon ,  CHAU, Robert S. ,  PILLARISETTY, Ravi

IPC: H01L29/78 ,  H01L21/318 ,  H01L21/336

CPC classification number: H01L21/8252 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/08 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed toward an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate and a buffer layer disposed over the semiconductor substrate. The buffer layer may have a plurality of openings formed therein. In embodiments, the IC die may further include a plurality of group III-Nitride structures. Individual group III-Nitride structures of the plurality of group III-Nitride structures may include a lower portion disposed in a respective opening of the plurality of openings and an upper portion disposed over the respective opening. In embodiments, the upper portion may include a base extending radially from sidewalls of the respective opening over a surface of the buffer layer to form a perimeter around the respective opening. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例针对集成电路（IC）管芯。 在实施例中，IC管芯可以包括半导体衬底和设置在半导体衬底之上的缓冲层。 缓冲层可以具有形成在其中的多个开口。 在实施例中，IC管芯可以进一步包括多个III族氮化物结构。 多个III族氮化物结构中的单个III族氮化物结构可以包括设置在多个开口的相应开口中的下部和设置在相应开口上的上部。 在实施例中，上部可以包括在缓冲层的表面上从相应开口的侧壁径向延伸的基部，以形成围绕相应开口的周边。 其他实施例可以被描述和/或要求保护。

公开(公告)号：EP3195364A1

公开(公告)日：2017-07-26

申请号：EP14902161.0

申请日：2014-09-18

Applicant: Intel Corporation

Inventor： DASGUPTA, Sansaptak ,  THEN, Han Wui ,  CHU-KUNG, Benjamin ,  RADOSAVLJEVIC, Marko ,  GARDNER, Sanaz K. ,  SUNG, Hoon ,  PILLARISETTY, Ravi ,  CHAU, Robert S.

IPC: H01L29/778

CPC classification number: H01L21/0265 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02521 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/7851

Abstract: III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.

Abstract translation: 描述了包括具有倾斜侧壁面的凸起的III-N半导体结构的III-N半导体异质结构。 在实施例中，采用有利于半极性倾斜侧壁小面的横向外延过度生长来将晶体缺陷从垂直传播弯曲为水平传播。 在实施例中，具有低缺陷密度表面的任意大的合并III-N半导体结构可以从暴露硅衬底的（100）表面的沟槽长出。 可以在凸起的III-N半导体结构上进一步形成III-N器件，例如III-N晶体管，同时可以在硅衬底的其他区域中形成硅基晶体管。

公开(公告)号：EP3123516A1

公开(公告)日：2017-02-01

申请号：EP14886974.6

申请日：2014-03-26

Applicant: Intel Corporation

Inventor： THEN, Han Wui ,  CHU-KUNG, Benjamin ,  DASGUPTA, Sansaptak ,  CHAU, Robert ,  SUNG, Seung Hoon ,  PILLARISETTY, Ravi ,  RADOSAVLJEVIC, Marko

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/0332 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7788

Abstract: Techniques related to III-N transistors having enhanced breakdown voltage, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a hardmask having an opening over a substrate, a source, a drain, and a channel between the source and drain, and a portion of the source or the drain disposed over the opening of the hardmask.

Abstract translation: 讨论了与具有增强的击穿电压的III-N晶体管相关的技术，并入这种晶体管的系统及其形成方法。 这种晶体管包括在衬底，源极，漏极以及源极和漏极之间的通道以及位于硬掩模的开口上的源极或漏极的一部分的开口的硬掩模。

公开(公告)号：EP3123497A1

公开(公告)日：2017-02-01

申请号：EP14886790.6

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： METZ, Matthew, V. ,  KAVALIEROS, Jack, T. ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  CHU-KUNG, Benjamin ,  RADOSAVLJEVIC, Marko ,  THEN, Han Wui ,  PILLARISETTY, Ravi ,  CHAU, Robert, S.

IPC: H01L21/20 ,  H01L21/18

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.

Abstract translation: 实施例包括基于III-V材料的器件，包括：在硅衬底上的基于第一III-V材料的缓冲层; 在第一III-V材料基缓冲层上的第二III-V材料基缓冲层，第二III-V材料包括铝; 以及在第二III-V材料基缓冲层上的基于III-V材料的器件沟道层。 另一个实施例包括上述主题，第一和第二III-V材料基缓冲层各自具有等于基于III-V材料的器件沟道层的晶格参数。 其他实施例包括在本文中。

公开(公告)号：EP3050111A1

公开(公告)日：2016-08-03

申请号：EP13894331.1

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： MUKHERJEE, Niloy ,  RADOSAVLJEVIC, Marko ,  KAVALIEROS, Jack T. ,  PILLARISETTY, Ravi ,  GOEL, Niti ,  LE, Van H. ,  DEWEY, Gilbert ,  CHU-KUNG, Benjamin

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7853 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/02538 ,  H01L29/0673 ,  H01L29/0688 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/78696

Abstract: An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.

Abstract translation: 一种包括半导体本体的装置，包括沟道区和设置在沟道区的相对侧上的结区，所述半导体本体包括包括第一带隙的第一材料; 以及包括第二材料的多个纳米线，所述第二材料包括不同于所述第一带隙的第二带隙，所述多个纳米线设置在穿过所述第一材料的分开的平面中，使得所述第一材料围绕所述多个纳米线中的每一个; 以及设置在通道区域上的栅极堆叠。 一种方法，包括在衬底上方的分离平面中形成多个纳米线，所述多个纳米线中的每一个包括包括第一带隙的材料; 在所述多个纳米线中的每一个周围分别形成包层材料，所述包层材料包括第二带隙; 聚结包层材料; 以及在所述包层材料上设置栅极堆叠。