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1.发明公开Cache coherent network adapter for scalable shared memory processing systems 失效可扩展的数据处理系统Cachekohärentes网络适配器具有共享存储器，
公开(公告)号：EP0890904A3
公开(公告)日：2003-08-27
申请号：EP98305159.0
申请日：1998-06-30
CPC分类号： G06F12/0813
摘要： A shared memory parallel processing system interconnected by a multi-stage network (20) combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently across the network. The system configuration techniques include a systematic method for partitioning and controlling the memory (54) in relation to local verses remote accesses and changeable verses unchangeable data. Most of the special-purpose hardware is implemented in the memory controller (210) and network adapter (10), which implements three send FIFOs (40, 41 and 42) and three receive FIFOs (44, 45 and 46) at each node (34) to segregate and handle efficiently invalidate functions, remote stores, and remote accesses requiring cache coherency. The segregation of these three functions into different send and receive FIFOs greatly facilitates the cache coherency function over the network. In addition, the network itself is tailored to provide the best efficiency for remote accesses.
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2.发明公开
公开(公告)号：EP0588745A1
公开(公告)日：1994-03-23
申请号：EP93480109.3
申请日：1993-07-30
发明人： Olnowich, Howard Thomas , Lusch, Robert Francis , Jabusch, John David , Maniguet, Michael Anthony
CPC分类号： H04L49/3081 , G06F11/261 , G06F13/4022 , G06F15/17337 , G06F15/17375 , G06F15/17393 , H04J2203/0005 , H04L1/0057 , H04L7/0338 , H04L12/18 , H04L12/1881 , H04L49/101 , H04L49/1523 , H04L49/253 , H04L49/254 , H04L49/256 , H04L49/357 , H04L49/40 , H04L69/08 , H04L69/18 , H04Q11/0001 , H04Q11/0066 , H04Q11/0478
摘要： Disclosed is multi-media switching apparatus for performing digital, analog, and/or optical communications amongst multiple nodes over switching networks. The key aspect of the present invention is the full parallel aspect of the switching apparatus which supports n simultaneously, low-latency connections, where n is the number of functional elements interconnected by the switching network. Any of the n simultaneous transmissions can be digital, analog, or optical in any proportion. In addition, the present invention can also serve as a high-speed distributed controller for the purpose of selecting analog or optical switches for information transfer between elements of the system.
摘要翻译： 公开了用于通过交换网络在多个节点之间执行数字，模拟和/或光通信的多媒体交换设备。 本发明的关键方面是支持n个同时低延迟连接的交换设备的完全并行方面，其中n是由交换网络互连的功能元件的数量。 任何n个同时传输可以是数字，模拟或光学任何比例。 此外，本发明还可以用作高速分布式控制器，用于选择用于在系统的元件之间进行信息传递的模拟或光学开关。
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公开(公告)号：EP0217023A3
公开(公告)日：1989-07-26
申请号：EP86109879.6
申请日：1986-07-18
IPC分类号： G06F9/38
摘要： A pipelined instruction execution system including a microstore (20a) for storing sequences of microinstruction addresses associated with each macroinstruction, a nanostore (20b) for randomly storing unique microinstructions, and an execution unit (30) for executing the microinstructions is provided with a no-op/prefetch apparatus (50), which prevents a microinstruction address, stored in the microstore, from accessing the nanostore and forces a no-op address into the nanostore when the execution unit executes a conditional microbranch instruction. During the execution of the no-op microinstruction in the execution unit, the no-op/prefetch apparatus permits either the next sequential microinstruction address following the conditional microbranch instruction to access the nanostore or another non-sequential microinstruction address to access the nanostore, the selection of the next sequential microinstruction address or said another non-sequential microinstruction depending upon the outcome of the execution of the conditional microbranch instruction by the execution unit.
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4.发明公开Cache coherent network adapter for scalable shared memory processing systems 失效可扩展的数据处理系统Cachekohärentes网络适配器具有共享存储器，
公开(公告)号：EP0890904A2
公开(公告)日：1999-01-13
申请号：EP98305159.0
申请日：1998-06-30
IPC分类号： G06F12/08
CPC分类号： G06F12/0813
摘要： A shared memory parallel processing system interconnected by a multi-stage network (20) combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently across the network. The system configuration techniques include a systematic method for partitioning and controlling the memory (54) in relation to local verses remote accesses and changeable verses unchangeable data. Most of the special-purpose hardware is implemented in the memory controller (210) and network adapter (10), which implements three send FIFOs (40, 41 and 42) and three receive FIFOs (44, 45 and 46) at each node (34) to segregate and handle efficiently invalidate functions, remote stores, and remote accesses requiring cache coherency. The segregation of these three functions into different send and receive FIFOs greatly facilitates the cache coherency function over the network. In addition, the network itself is tailored to provide the best efficiency for remote accesses.
摘要翻译： 通过多级网络（20）相互连接的共享存储器的并行处理系统结合新的系统配置与技术专用硬件来提供跨网络远程存储器访问，而在网络上有效地控制高速缓存一致性。 系统配置技术包括为分区和一个系统的方法来控制相对于本地节远程访问和多变经文不可改变的数据存储器（54）。 大部分的专用硬件的是在存储器控制器（210）和网络适配器（10），这实现了三个发送的FIFO（40，41和42）和三个实施接收FIFO（44，45和46）中的每个节点（ 34）以分离和手柄高效无效的功能，远程存储和远程访问要求的高速缓存一致性。 本文的三个功能分离到不同的发送和接收FIFO极大地方便了网络的高速缓存一致性功能。 此外，网络本身的目的在于提供用于远程访问的最佳效率。
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5.发明公开
公开(公告)号：EP0588030A3
公开(公告)日：1995-01-25
申请号：EP93111912.7
申请日：1993-07-26
发明人： Olnowich, Howard Thomas , Dotson, Michael Wayland , Feeney, James William , Fisher, Michael Hans , Jabusch, John David , Lusch, Robert Francis , Maniguet, Michael Anthony
CPC分类号： H04L12/40019 , G06F13/385 , G06F13/4022 , G06F15/17375 , H04L12/1881 , H04L12/40 , H04L12/40032 , H04L49/153
摘要： Disclosed is a conversion apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel (IBM Trade mark) bus, to more progressive switch interconnection protocol and architecture. The ivention extends existing the bus-based architecture to perform parallel and clustering functions by enabling the interconnection of thousands of processors. A conversion apparatus is disclosed for controlling the transfer of data messages from one nodal element across a switch network to another nodal element by using direct memory access capabilities controlled by intelligent bus masters. This approach does not require interactive support from teh processor at either nodal element during the message transmision, and frees up both processors to perform other tasks. In addition, the communication media is switch-based and is fully parallel, supporting n transmissions simultaneously, where n is the number of nodes interconnected by the switching network.
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公开(公告)号：EP0588025A3
公开(公告)日：1994-09-07
申请号：EP93111755.0
申请日：1993-07-22
发明人： Olnowich, Howard Thomas , Fisher, Michael Hans , Lusch, Robert Francis , Maniguet, Michael Anthony , Saiyid, Omar Aziz
CPC分类号： G06F15/17375 , G06F11/261 , G06F13/4022 , G06F15/17337 , G06F15/17393 , H04J2203/0005 , H04L1/0057 , H04L7/0338 , H04L12/18 , H04L12/1881 , H04L49/256 , H04L49/3081 , H04L49/40 , H04L69/08 , H04L69/18 , H04Q11/0001 , H04Q11/0066 , H04Q11/0478
摘要： Disclosed is a modularly expandable switch-based planar apparatus for inserting multiple bus-based processor cards and/or expansion cards and interconnecting the said cards via a multi-stage switch network which resides on the invention planar. The switching network is built into the planar. The cards require no modification or change of any kind, since the connection to the planar is made as if the planar contained the standard MicroChannel interconnection. However, the disclosed planar implements bus converter units to convert the standard bus interface provided by the cards to the switch network interface, so that functions provided by the cards can communicate in parallel over the switch network.
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7.发明公开Selectable checking of message destinations in a switched parallel network 失效Vermittlungsnetz在einem parallelen的WählbareÜberprüfungvon Nachrichtenzielen。
公开(公告)号：EP0610582A2
公开(公告)日：1994-08-17
申请号：EP93120303.8
申请日：1993-12-16
IPC分类号： H04L12/56
CPC分类号： H04L12/1877 , H04L45/00
摘要： A method and hardware apparatus provide a fault tolerant and flexible multi-stage network addressing scheme for transmitting a message with a header containing control bits for selecting from various destination checking functions to be performed. Upon arrival of the message at a node, destination checking is performed or not in response to the message's header. If destination checking is not performed, or if destination checking is performed and indicates that the node is the desired destination for the message, the message is accepted. If destination checking is performed and indicates that the node is not the desired destination for the message, the message is rejected. Destination checking is disabled during address assignment, broadcasting and multi-casting, and replaced with one's complement-based verification of the sending node.
摘要翻译： 方法和硬件设备提供容错和灵活的多级网络寻址方案，用于发送具有包含用于从要执行的各种目的地检查功能进行选择的控制位的报头的消息。 在消息到达节点时，响应于消息的报头执行目的地检查。 如果不执行目的地检查，或者执行目的地检查，并指示节点是消息的所需目的地，则接受该消息。 如果执行目的地检查，并指示该节点不是该消息的所需目的地，则该消息被拒绝。 在地址分配，广播和多播过程中禁用目的地检查，并替换为发送节点的补码验证。
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公开(公告)号：EP0588104A2
公开(公告)日：1994-03-23
申请号：EP93113397.9
申请日：1993-08-23
IPC分类号： G06F15/16
CPC分类号： H04L49/3081 , G06F11/261 , G06F13/4022 , G06F15/17337 , G06F15/17375 , G06F15/17393 , H04J2203/0005 , H04L1/0057 , H04L7/0338 , H04L12/18 , H04L12/1881 , H04L49/251 , H04L49/254 , H04L49/256 , H04L49/40 , H04L69/08 , H04L69/18 , H04Q11/0001 , H04Q11/0066 , H04Q11/0478
摘要： Disclosed is a new torus switch with low latency performance. The present invention improves the torus network connection time by providing the capability to try multipaths in one single high speed operation. This multipath approach can be directed at establishing a connection between two specific nodes over various alternate routes simultaneously. The invention is such that if only one route is available, the multipath approach will find that path instantanteously and establish the desired connection with minimal latency. If several links are available, the multipath method establishes the desired connection over only one of the available links and leaves the other options free to be used by other connections. In addition, routing at intermediate torus network stages will be a vast improvement of the wormhole approach.
摘要翻译： 公开了一种具有低延迟性能的新型环面交换机。 本发明通过提供在单个高速操作中尝试多路径的能力来改善环形网络连接时间。 该多路径方法可以针对同时在各种替代路由上建立两个特定节点之间的连接。 本发明使得如果只有一条路由可用，则多路径方法将立即找到该路径，并以最小延迟建立所需的连接。 如果有多个链接可用，则多路径方法通过只有一个可用链接建立所需的连接，并留下其他选项可供其他连接使用。 此外，在中间环网阶段的路由将是虫洞方法的巨大改进。
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公开(公告)号：EP0505779A3
公开(公告)日：1993-11-03
申请号：EP92103746.1
申请日：1992-03-05
发明人： Olnowich, Howard Thomas , Barker, Thomas Norman , Kogge, Peter Michael , Vandling III, Gilbert Clyde
CPC分类号： H04L1/0057 , G06F11/261 , G06F13/364 , G06F13/4022 , G06F15/17375 , G06F15/17393 , H03M9/00 , H04L7/0338 , H04L7/044 , H04L49/101 , H04L49/1515 , H04L49/1523 , H04L49/201 , H04L49/205 , H04L49/40 , H04L49/55 , H04Q11/0066 , H04Q11/0478
摘要： Disclosed is an implementation of a high priority path that is in addition to the normal low priority path through a multi-stage switching network. The high priority path is established at the quickest possible speed because the high priority command is stored at the switch stage involved and made on a priority basis as soon as output port required becomes available. In addition, a positive feedback is given to the node establishing the connection immediately upon the making of the connection so that it may proceed at the earliest possible moment. The high priority path is capable of processing multiple high priority pending requests, and resolving the high priority contention using a snapshot register which implements a rotating priority such that no one requesting device can ever be locked out or experience data starvation. A dual priority switching apparatus with input port connections to output port connections uses an asynchronous means to resolve contention under low priority and the absence of blockage conditions, and switches automatically to a priority driven synchronous means of resolving contention under the presence of blockage and high priority conditions. The disclosed improvement to the ALL-NODE (Asynchronous, Low Latency inter-NODE) Switch permits contention to be detected and resolved on chip in either a low or high priority mode, and yet the logic implementation is extremely simple and low in gate count, so the switch design is never gate limited. The protocol requires several parallel data lines plus four control lines so that the switching apparatus can used for networks having a plurality of nodes, each node having a plurality of input and output ports, with a a multiplexer control circuit for each output port for connecting any of I inputs to any of Z outputs, where I and Z can assume any unique value greater or equal to two, and a different priority level is assigned to a function. The switch has a single physical network path element over which either a low priority or high priority path can be established.
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10.发明公开Dual priority switching apparatus for simplex networks 失效Schnevorrichtung mit DoppelterPrioritätfürSimplex-Netzwerke。
公开(公告)号：EP0505779A2
公开(公告)日：1992-09-30
申请号：EP92103746.1
申请日：1992-03-05
发明人： Olnowich, Howard Thomas , Barker, Thomas Norman , Kogge, Peter Michael , Vandling III, Gilbert Clyde
CPC分类号： H04L1/0057 , G06F11/261 , G06F13/364 , G06F13/4022 , G06F15/17375 , G06F15/17393 , H03M9/00 , H04L7/0338 , H04L7/044 , H04L49/101 , H04L49/1515 , H04L49/1523 , H04L49/201 , H04L49/205 , H04L49/40 , H04L49/55 , H04Q11/0066 , H04Q11/0478
摘要： Disclosed is an implementation of a high priority path that is in addition to the normal low priority path through a multi-stage switching network. The high priority path is established at the quickest possible speed because the high priority command is stored at the switch stage involved and made on a priority basis as soon as output port required becomes available. In addition, a positive feedback is given to the node establishing the connection immediately upon the making of the connection so that it may proceed at the earliest possible moment. The high priority path is capable of processing multiple high priority pending requests, and resolving the high priority contention using a snapshot register which implements a rotating priority such that no one requesting device can ever be locked out or experience data starvation. A dual priority switching apparatus with input port connections to output port connections uses an asynchronous means to resolve contention under low priority and the absence of blockage conditions, and switches automatically to a priority driven synchronous means of resolving contention under the presence of blockage and high priority conditions. The disclosed improvement to the ALL-NODE (Asynchronous, Low Latency inter-NODE) Switch permits contention to be detected and resolved on chip in either a low or high priority mode, and yet the logic implementation is extremely simple and low in gate count, so the switch design is never gate limited. The protocol requires several parallel data lines plus four control lines so that the switching apparatus can used for networks having a plurality of nodes, each node having a plurality of input and output ports, with a a multiplexer control circuit for each output port for connecting any of I inputs to any of Z outputs, where I and Z can assume any unique value greater or equal to two, and a different priority level is assigned to a function. The switch has a single physical network path element over which either a low priority or high priority path can be established.
摘要翻译： 公开了除了通过多级交换网络的正常低优先级路径之外的高优先级路径的实现。 高优先级路径以尽可能快的速度建立，因为高优先级命令存储在所涉及的切换阶段，并且一旦需要输出端口可用就优先进行。 另外，在建立连接时立即建立连接的节点，使得它可以在尽可能早的时刻进行正向的反馈。 高优先级路径能够处理多个高优先级待处理请求，并且使用实现旋转优先级的快照寄存器来解决高优先权争用，使得没有一个请求设备可以被锁定或经历数据不足。 具有输入端口连接到输出端口连接的双重优先级交换设备使用异步方式来在低优先级和没有阻塞条件的情况下解决争用，并且在阻塞和高优先级存在的情况下自动切换到优先级驱动的同步方式来解决争用 条件。 ALL-NODE（异步，低延迟节点）交换机的公开改进允许在低优先级或高优先级模式下在芯片上检测和解决争用，然而逻辑实现非常简单且门计数低， 所以开关设计从来不限于门限。 该协议需要几条并行数据线加上四条控制线，使得交换设备可用于具有多个节点的网络，每个节点具有多个输入和输出端口，每个输出端口具有多路复用器控制电路，用于连接任何 我输入任何Z输出，其中I和Z可以采用大于或等于2的任何唯一值，并且将不同的优先级分配给一个功能。 交换机具有单个物理网络路径元素，通过该单个物理网络路径元素可以建立低优先级或高优先级路径。
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