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    VERTICAL TRANSISTOR DRAM CELL AND METHOD OF MAKING THE SAME
    2.
    发明公开
    VERTICAL TRANSISTOR DRAM CELL AND METHOD OF MAKING THE SAME 审中-公开
    具有垂直电晶体和方法DRAM CELL生产同样

    公开(公告)号：EP1328972A2

    公开(公告)日：2003-07-23

    申请号：EP01968929.8

    申请日：2001-09-19

    申请人： Infineon Technologies North America Corp.

    发明人： SHEN, Hua

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10864 ,  H01L27/10876 ,  H01L27/10885

    摘要： An integrated circuit comprising a vertically oriented device formed with a substantially SELF ALIGNED process, in which the trench, active area (e.g., 128, 228), and gate (e.g., 132, 232) of a DRAM cell may be formed using a minimal number of masks and lithographic steps. Using this process, a DRAM cell comprising a vertical transistor and a buried word line (e.g., 132, 232) may be formed. A gate dielectric (e.g., 130, 230) may be disposed adjacent the active area, and the portion of the buried word line adjacent the gate dielectric may function as the vertically oriented gate for the vertical transistor. The DRAM memory cell may comprise one of a variety of capacitors, such a trench capacitor underlying the vertical transistor, or a stack capacitor (e.g., 241) overlying the vertical transistor. When a stack capacitor is used, a buried bit line (e.g., 208) underlying the vertical transistor may also be used.