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公开(公告)号：EP1279188A1
公开(公告)日：2003-01-29
申请号：EP01935012.3
申请日：2001-05-02
发明人： WANG, Yun-Yu , JAMMY, Rajarao , KIMBALL, Lee, J. , KOTECKI, David, E. , LIAN, Jenny , LIN, Chenting , MILLER, John, A. , NAGEL, Nicholas , SHEN, Hua , WILDMAN, Horatio, S.
IPC分类号： H01L21/02
摘要： A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second electrode portion is provided.
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公开(公告)号：EP1397830A2
公开(公告)日：2004-03-17
申请号：EP01988335.4
申请日：2001-12-19
发明人： BOETTCHER, Steven, H. , HO, Herbert, L. , HOINKIS, Mark , LEE, Hyun, Koo , WANG, Yun-Yu , WONG, Kwong, Hon
IPC分类号： H01L21/44
CPC分类号： H01L21/76846 , H01L21/76858 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer (42) of Ti, followed by a conformal liner layer (46) of CVD TiN, followed in turn by a final liner layer (48) of TA or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the copper to an acceptable amount.
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公开(公告)号：EP1397830B1
公开(公告)日：2010-02-03
申请号：EP01988335.4
申请日：2001-12-19
发明人： BOETTCHER, Steven, H. , HO, Herbert, L. , HOINKIS, Mark , LEE, Hyun, Koo , WANG, Yun-Yu , WONG, Kwong, Hon
IPC分类号： H01L21/768
CPC分类号： H01L21/76846 , H01L21/76858 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
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4.发明授权A METHOD FOR DEPOSITING A METAL LAYER ON A SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING A CAPPING LAYER 有权用于沉积金属层上的半导体INTERKONNEKTSTRUKTUR具有表面的方法
公开(公告)号：EP1570517B1
公开(公告)日：2010-06-02
申请号：EP03796085.3
申请日：2003-12-08
发明人： CLEVENGER, Larry , DALTON, Timothy , HOINKIS, Mark , KALDOR, Steffen , KUMAR, Kaushik , LA TULIPE, Douglas, Jr. , SEO, Soon-Cheon , SIMON, Andrew , WANG, Yun-Yu , YANG, Chih-Chao , YANG, Haining
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76805 , H01L21/76807 , H01L21/76834 , H01L21/76835 , H01L21/76844 , H01L21/76847 , H01L21/76865
摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.
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公开(公告)号：EP1279188B1
公开(公告)日：2006-09-06
申请号：EP01935012.3
申请日：2001-05-02
发明人： WANG, Yun-Yu , JAMMY, Rajarao , KIMBALL, Lee, J. , KOTECKI, David, E. , LIAN, Jenny , LIN, Chenting , MILLER, John, A. , NAGEL, Nicolas , SHEN, Hua , WILDMAN, Horatio, S.
IPC分类号： H01L21/02
摘要： A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second electrode portion is provided.
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6.发明公开A METHOD FOR DEPOSITING A METAL LAYER ON A SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING A CAPPING LAYER 有权用于沉积金属层上的半导体INTERKONNEKTSTRUKTUR具有表面的方法
公开(公告)号：EP1570517A1
公开(公告)日：2005-09-07
申请号：EP03796085.3
申请日：2003-12-08
发明人： CLEVENGER, Larry , DALTON, Timothy , HOINKIS, Mark , KALDOR, Steffen , KUMAR, Kaushik , LA TULIPE, Douglas, Jr. , SEO, Soon-Cheon , SIMON, Andrew , WANG, Yun-Yu , YANG, Chih-Chao , YANG, Haining
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76805 , H01L21/76807 , H01L21/76834 , H01L21/76835 , H01L21/76844 , H01L21/76847 , H01L21/76865
摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.
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公开(公告)号：EP1943675A1
公开(公告)日：2008-07-16
申请号：EP06793278.0
申请日：2006-09-06
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/76834 , H01L21/76832 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned opening, and a dielectric cap overlying the metal feature. The dielectric cap has an internal tensile stress, the stress helping to avoid electromigration from occurring in a direction away from the metal line, especially when the metal line has tensile stress.
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公开(公告)号：EP1943675B1
公开(公告)日：2013-03-20
申请号：EP06793278.0
申请日：2006-09-06
发明人： YANG, Chih-Chao IBM United Kingdom Limited , CHANDA, Kaushik , CLEVENGER, Lawrence , WANG, Yun-Yu , YANG, Daewon
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L21/76834 , H01L21/76832 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
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公开(公告)号：EP1356498A1
公开(公告)日：2003-10-29
申请号：EP01990114.9
申请日：2001-12-13
发明人： ENGEL, Brett, H. , HOINKIS, Mark , MILLER, John, A. , SEO, Soon-Cheon , WANG, Yun-Yu , WONG, Hon Wong
IPC分类号： H01K3/10
CPC分类号： H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： In integrated circuits having copper interconnect (30, 50) and low-k interlayer dielectrics (40), a problem of open circuits after heat treatment was discovered and solved bz the use of a first liner layer of Cr (42), followed by a conformal liner layer of CVD TiN (46), followed in turn bz a final liner layer of Ta or TaN (48), thus improving adhesion between the via (50) and the underlying copper layer (30) while maintianing low resistance.
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10.发明公开INTERCONNECT STRUCTURE HAVING ENHANCED ELECTROMIGRATION RELIABILITY AND A METHOD OF FABRICATING SAME 审中-公开具有产生改进的电荷迁移可靠性和过程连接结构
公开(公告)号：EP2095409A1
公开(公告)日：2009-09-02
申请号：EP07842115.3
申请日：2007-09-10
发明人： YANG, Chih-Chao , WANG, Ping-Chuan , WANG, Yun-Yu
IPC分类号： H01L21/44
CPC分类号： H01L21/76847 , H01L23/5226 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by incorporating a EM preventing liner (66) at least partially within a metal interconnect. In one embodiment, a 'U-shaped' EM preventing liner (66) is provided that abuts a diffusion barrier that separates conductive material (64, 68) from the dielectric material (54B). In another embodiment, a space is located between the 'U-shaped' EM preventing liner and the diffusion barrier. In yet another embodiment, a horizontal EM liner that abuts the diffusion barrier is provided. In yet a further embodiment, a space exists between the horizontal EM liner and the diffusion barrier.
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