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公开(公告)号：EP1279188B1
公开(公告)日：2006-09-06
申请号：EP01935012.3
申请日：2001-05-02
发明人： WANG, Yun-Yu , JAMMY, Rajarao , KIMBALL, Lee, J. , KOTECKI, David, E. , LIAN, Jenny , LIN, Chenting , MILLER, John, A. , NAGEL, Nicolas , SHEN, Hua , WILDMAN, Horatio, S.
IPC分类号： H01L21/02
摘要： A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second electrode portion is provided.
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2.发明公开USING METAL/METAL NITRIDE BILAYERS AS GATE ELECTRODES IN SELF-ALIGNED AGGRESSIVELY SCALED CMOS DEVICES 有权金属/金属氮化物双层AS栅极电极的自对准AGGRESSIVE缩放CMOS组件使用
公开(公告)号：EP1872407A2
公开(公告)日：2008-01-02
申请号：EP06750529.7
申请日：2006-04-18
发明人： CARTIER, Eduard, A. , COPEL, Matthew, W. , DORIS, Bruce, B. , JAMMY, Rajarao , KIM, Young-Hee , LINDER, Barry, P. , NARAYANAN, Vijay , PARUCHURI, Vamsi, K. , WONG, Keith, Kwong, Hon
IPC分类号： H01L29/76
CPC分类号： H01L21/823842
摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
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3.发明公开GATE STACK ENGINEERING BY ELECTROCHEMICAL PROCESSING UTILIZING THROUGH-GATE-DIELECTRIC CURRENT FLOW 审中-公开栅极堆叠技术，通过电化学处理与电流流过栅极电介质
公开(公告)号：EP1846947A1
公开(公告)日：2007-10-24
申请号：EP05852630.2
申请日：2005-12-02
发明人： VEREECKEN, Philippe, M. , BASKER, Veeraraghavan , CABRAL, Cyril, Jr. , COOPER, Emanuel, I. , DELIGIANNI, Hariklia , FRANK, Martin, M. , JAMMY, Rajarao , PARUCHURI, Vamsi, Krishna , SAENGER, Katherine, L. , SHAO, Xiaoyan
IPC分类号： H01L21/302 , H01L29/745
CPC分类号： H01L21/2885 , C25D3/50 , C25D5/02 , C25D5/024 , C25D5/54 , C25D7/123 , C25D9/04 , C25F3/14 , H01L21/28079 , H01L21/28114 , H01L21/76885 , H01L29/513 , H01L29/517 , H01L29/78648
摘要： A method for electroplating a gate metal (9) or other conducting or semiconducting material on a gate dielectric (2) is provided. The method involves selecting a substrate (3, 4), dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be generated at an interface between the dielectric layer and the electrolyte solution or melt.
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4.发明公开INTRODUCTION OF METAL IMPURITY TO CHANGE WORKFUNCTION OF CONDUCTIVE ELECTRODES 审中-公开引言金属杂质修订工作职能引出电极
公开(公告)号：EP1974372A2
公开(公告)日：2008-10-01
申请号：EP07716303.8
申请日：2007-01-03
发明人： CHUDZIK, Michael, P. , DORIS, Bruce, B. , GUHA, Supratik , JAMMY, Rajarao , NARAYANAN, Vijay , PARUCHURI, Vamsi, K. , WANG, Yun, Y. , KWONG HON WONG, Keith
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823828 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal- oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material.
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公开(公告)号：EP1687457A2
公开(公告)日：2006-08-09
申请号：EP04812387.1
申请日：2004-11-29
IPC分类号： C22C32/00
CPC分类号： H01L29/4966 , H01L21/823842
摘要： A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET (210) that comprises a gate electrode (180) comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal (150) and a carbide of a metal.
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6.发明授权Semiconductor structure comprising a HfSiN metal gate and method of forming the same 有权具有金属栅极HfSiN和制造工艺的半导体结构
公开(公告)号：EP1836732B1
公开(公告)日：2011-09-28
申请号：EP05826298.1
申请日：2005-12-02
发明人： CALLEGARI, Alessandro C. , FRANK, Martin M. c/o IBM United Kingdom Limited, , JAMMY, Rajarao , LACEY, Dianne L. , MCFEELY, Fenton R. , ZAFAR, Sufi
IPC分类号： H01L27/088 , H01L21/28 , H01L29/49
CPC分类号： H01L29/4966 , H01L21/28088 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6659
摘要： A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000°C), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.
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7.发明公开LOW THRESHOLD VOLTAGE SEMICONDUCTOR DEVICE WITH DUAL THRESHOLD VOLTAGE CONTROL MEANS 审中-公开用双阈值电压控制装置低阈值电压半导体部件
公开(公告)号：EP1949447A2
公开(公告)日：2008-07-30
申请号：EP06825854.0
申请日：2006-10-12
发明人： CARTER, Eduard, A. , COPEL, Matthew, W. , FRANK, Martin, M. , GOUSEV, Evgeni, P. , JAMISON, Paul, C. , JAMMY, Rajarao , LINDER, Barry, P. , NARAYANAN, Vijay
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/28238 , H01L21/823807 , H01L29/105 , H01L29/1083 , H01L29/517 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.
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公开(公告)号：EP1279188A1
公开(公告)日：2003-01-29
申请号：EP01935012.3
申请日：2001-05-02
发明人： WANG, Yun-Yu , JAMMY, Rajarao , KIMBALL, Lee, J. , KOTECKI, David, E. , LIAN, Jenny , LIN, Chenting , MILLER, John, A. , NAGEL, Nicholas , SHEN, Hua , WILDMAN, Horatio, S.
IPC分类号： H01L21/02
摘要： A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second electrode portion is provided.
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公开(公告)号：EP1687457B1
公开(公告)日：2010-03-10
申请号：EP04812387.1
申请日：2004-11-29
IPC分类号： H01L21/8238 , C23C14/06 , C23C16/32
CPC分类号： H01L29/4966 , H01L21/823842
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10.发明公开SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH K DIELECTRICS 有权层层壁垒的选择性实施旨在实现阈值电压控制在CMOS元件具有高K电介质的生产
公开(公告)号：EP1766691A2
公开(公告)日：2007-03-28
申请号：EP05732384.2
申请日：2005-03-30
发明人： BOJARCZUK, Nestor A., Jr. , CABRAL, Cyril, Jr. , Cartier, Eduard A. , COPEL, Matthew W. , FRANK, Martin M. , GOUSEV, Evgeni P. , GUHA, Supratik , JAMMY, Rajarao , Narayanan, Vijay , Paruchuri, Vamsi K.
IPC分类号： H01L31/113
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprisisng an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be A1N or A1OxNY. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HC1/H2O2 peroxide solution.
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