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12 条记录 (耗时 0.009 秒)

    CLOCK GATING USING A DELAY CIRCUIT
    2.
    发明公开
    CLOCK GATING USING A DELAY CIRCUIT 审中-公开

    公开(公告)号：EP3329341A1

    公开(公告)日：2018-06-06

    申请号：EP16741181.8

    申请日：2016-06-27

    申请人： Qualcomm Incorporated

    发明人： HAMDAN, Fadi Adel

    IPC分类号： G06F1/10 ,  G06F1/32 ,  H03K5/00

    CPC分类号： H03K3/0372 ,  G06F1/10 ,  G06F1/12 ,  G06F1/3237 ,  G06F13/362 ,  H03K3/0375 ,  H03K5/131 ,  H03K5/135 ,  H03K2005/00013 ,  H03K2005/00058 ,  Y02D10/128

    摘要： An apparatus includes a latch of a clock gating circuit (CGC). The latch is configured to generate a first signal in response to a clock signal. The apparatus further includes a delay circuit of the CGC. The delay circuit is configured to receive the clock signal and to generate a second signal based on the clock signal and the first signal. The apparatus further includes an output circuit of the CGC. The output circuit is coupled to the delay circuit and to the latch. The output circuit is configured to generate a master clock signal based on the clock signal and the second signal. An edge of the master clock signal is delayed with respect to an edge of the clock signal based on a delay characteristic associated with a slave clock signal.

    SIGNAL TRANSMISSION CIRCUIT, FIELD DEVICE, AND PLANT CONTROL SYSTEM
    4.
    发明公开
    SIGNAL TRANSMISSION CIRCUIT, FIELD DEVICE, AND PLANT CONTROL SYSTEM 审中-公开
    信号传输电路，现场设备和工厂控制系统

    公开(公告)号：EP3282585A1

    公开(公告)日：2018-02-14

    申请号：EP17183466.6

    申请日：2017-07-27

    申请人： Yokogawa Electric Corporation

    发明人： Endo, Tatsuro ,  Wada, Masami

    IPC分类号： H03K17/78 ,  H04L25/02

    CPC分类号： G05B19/4183 ,  G05B2219/40237 ,  H03K5/01 ,  H03K19/21 ,  H03K2005/00013 ,  H04L25/0266

    摘要： A signal transmission circuit includes a first photocoupler to which a transmission signal is input, an edge detection circuit which is disposed in a primary side of the first photocoupler, the edge detection circuit being configured to detect a rising edge and a falling edge of the transmission signal, and an edge demodulation circuit which is disposed in a secondary side of the first photocoupler, the demodulation circuit being configured to demodulate the transmission signal by using only one of the rising edge and the falling edge of an edge detection signal output from the edge detection circuit via the first photocoupler.

    摘要翻译： 一种信号传输电路，包括：第一光电耦合器，被输入传输信号;第一光电耦合器，被配置在第一光电耦合器的一次侧，边缘检测电路被配置为检测传输的上升沿和下降沿 信号;以及边缘解调电路，其设置在所述第一光电耦合器的次级侧，所述解调电路被配置为通过仅使用从所述边缘输出的边缘检测信号的上升沿和下降沿中的一个来解调所述发送信号 检测电路通过第一光电耦合器。

    DTC-BASED PLL AND METHOD FOR OPERATING THE DTC-BASED PLL
    6.
    发明公开
    DTC-BASED PLL AND METHOD FOR OPERATING THE DTC-BASED PLL 审中-公开
    基于DTC的PLL和用于操作基于DTC的PLL的方法

    公开(公告)号：EP3249817A1

    公开(公告)日：2017-11-29

    申请号：EP17172898.3

    申请日：2017-05-24

    申请人： IMEC vzw ,  Stichting IMEC Nederland ,  Vrije Universiteit Brussel

    发明人： MARKULIC, Nereo ,  LIU, Yao-Hong ,  CRANINCKX, Jan

    IPC分类号： H03L7/197 ,  H03L7/081 ,  H03L7/099

    CPC分类号： H03L7/085 ,  H03K5/159 ,  H03K2005/00013 ,  H03L7/081 ,  H03L7/0991 ,  H03L7/197 ,  H03L7/1976 ,  H03L2207/50

    摘要： The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a stream of pseudo-random offsets, i.e. pseudo-random numbers, to the delay value. The offset is such that the target output of the phase detector remains substantially unchanged.

    摘要翻译： 本公开提供了一种锁相环PLL，用于将输出信号锁相到参考信号。 PLL包括将参考信号提供给相位检测器的第一输入端的参考路径，将PLL的输出信号作为反馈信号提供给相位检测器的第二输入端的反馈回路，基于相位检测器产生输出信号的可控制振荡器 至少在参考和反馈信号之间的相位差上，数字 - 时间转换器DTC延迟在第一和第二输入之一提供的信号，延迟计算路径用于计算DTC延迟值。 该PLL还包括一个随机化单元，用于产生一个伪随机偏移流，即伪随机数，并将其添加到该延迟值。 偏移量使得相位检测器的目标输出保持基本不变。

    EDGE-AWARE SYNCHRONIZATION OF A DATA SIGNAL
    8.
    发明公开
    EDGE-AWARE SYNCHRONIZATION OF A DATA SIGNAL 审中-公开
    数据信号的边缘意识同步

    公开(公告)号：EP3230818A1

    公开(公告)日：2017-10-18

    申请号：EP15867374.9

    申请日：2015-11-11

    申请人： Intel Corporation

    发明人： CHEN, Gregory K. ,  ANDERS, Mark A. ,  KAUL, Himanshu

    IPC分类号： G06F1/12

    CPC分类号： H03K5/135 ,  G06F5/10 ,  G11C8/18 ,  G11C19/287 ,  H03K2005/00013

    摘要： A signal comprising a first edge and a second edge is received. The first edge of the signal is synchronized with a first clock and the synchronized first edge of the signal is passed to an output. The synchronization results in a delay of the first edge of the signal. The second edge of the signal is passed to the output. The passed second edge of the signal has a delay that is less than the delay of the first edge of the signal by at least one clock cycle of the first clock.

    摘要翻译： 接收包括第一边缘和第二边缘的信号。 信号的第一个边沿与第一个时钟同步，信号的同步的第一个边沿传送到输出。 同步会导致信号的第一个边沿延迟。 信号的第二个边沿被传递到输出端。 信号的第二个边沿的延迟小于第一个时钟周期的至少一个信号的第一个边沿的延迟。

    INTEGRATED CIRCUIT DYNAMIC DE-AGING
    10.
    发明公开
    INTEGRATED CIRCUIT DYNAMIC DE-AGING 审中-公开
    DYNAMISCHE ENTALTERUNG EINER INTEGRIERTEN SCHALTUNG

    公开(公告)号：EP3127239A1

    公开(公告)日：2017-02-08

    申请号：EP15713821.5

    申请日：2015-03-04

    申请人： Qualcomm Incorporated

    发明人： LIU, Jonathan ,  IBRAHIMOVIC, Jasmin Smaila ,  DIFFENDERFER, Jan Christian ,  AUYON, Carlos

    IPC分类号： H03K3/03 ,  G01R31/317 ,  H03K19/003

    CPC分类号： G05B11/01 ,  G01R31/2882 ,  G01R31/31725 ,  H03K3/012 ,  H03K3/0315 ,  H03K5/01 ,  H03K19/00384 ,  H03K2005/00013 ,  Y10T307/852

    摘要： An integrated circuit dynamically compensates for circuit aging by measuring the aging with an aging sensor. The aging sensor uses the same circuit to measure circuit speeds in both aged and un-aged conditions. An example aging sensor includes two delay lines. The delay lines are controlled to be in a static aging state or the delay lines are coupled to form a ring oscillator that can operate in an aged state where the frequency is slowed by aging or in an un-aged state where the frequency is not slowed by aging. The integrated circuit uses the aging measurements for dynamic voltage and frequency scaling. The dynamic voltage and frequency scaling uses a table of operating frequencies and corresponding voltage that is periodically updated based on the aging measurements. The integrated circuit use information about the relationship between the aging measurements and circuit performance to update the table.

    摘要翻译： 集成电路通过老化传感器测量老化来动态地补偿电路老化。 老化传感器使用相同的电路来测量老化和非老化条件下的电路速度。 示例性老化传感器包括两个延迟线。 延迟线被控制为处于静态老化状态，或者延迟线被耦合以形成环形振荡器，其可以在老化状态下工作，其中频率由于老化而衰减或处于不老化的状态，其中频率没有减慢 通过老化 集成电路使用老化测量动态电压和频率缩放。 动态电压和频率缩放使用基于老化测量值周期更新的工作频率表和相应的电压表。 集成电路使用有关老化测量和电路性能之间关系的信息来更新表。