公开(公告)号：EP4290565A1

公开(公告)日：2023-12-13

申请号：EP23171920.4

申请日：2023-05-05

申请人： Intel Corporation

发明人： RESHOTKO, Miriam ,  KARPOV, Elijah V. ,  ANDERS, Mark A. ,  AULUCK, Gauri ,  SUNDARARAJAN, Shakuntala ,  Makowski, Michael ,  BARRETT, Caleb

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/522

摘要： Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization. Adjacent interconnect features may comprise a plurality of first interconnect lines with spaces therebetween. A dielectric material is over the first interconnect lines and within the spaces between the first interconnect lines. Resultant topography in the dielectric material defines a plurality of trenches between the first interconnect lines. The adjacent interconnect features further comprise a plurality of second interconnect lines interdigitated with the first interconnect lines that occupy at least a portion of the trenches between individual ones of the first interconnect lines.

公开(公告)号：EP3235194A1

公开(公告)日：2017-10-25

申请号：EP15870589.7

申请日：2015-11-19

申请人： INTEL Corporation

发明人： ANDERS, Mark A. ,  CHEN, Gregory K. ,  KAUL, Himanshu

IPC分类号： H04L12/771 ,  H04L12/931 ,  G06F13/14

CPC分类号： H04L45/72 ,  H04L45/16 ,  H04L45/60 ,  H04L47/33 ,  H04L49/109 ,  H04L49/25

摘要： A first packet and a first direction associated with the first packet are received. The first packet is forwarded to an output port of a plurality of output ports of the first router based on the first direction associated with the first packet. A second direction associated with the first packet is determined. The second direction is based at least on an address of the first packet. The first packet and the second direction are forwarded through the output port of the first router to a second router.

摘要翻译： 接收与第一分组相关联的第一分组和第一方向。 基于与第一分组相关联的第一方向将第一分组转发到第一路由器的多个输出端口中的输出端口。 确定与第一分组相关联的第二方向。 第二方向至少基于第一分组的地址。 第一包和第二方向通过第一路由器的输出端口转发到第二路由器。

公开(公告)号：EP3235194B1

公开(公告)日：2020-11-04

申请号：EP15870589.7

申请日：2015-11-19

申请人： INTEL Corporation

发明人： ANDERS, Mark A. ,  CHEN, Gregory K. ,  KAUL, Himanshu

IPC分类号： H04L12/771 ,  H04L12/931 ,  G06F13/14 ,  H04L12/761 ,  H04L12/773 ,  H04L12/933 ,  H04L12/801 ,  H04L12/947

公开(公告)号：EP3234783B1

公开(公告)日：2019-09-04

申请号：EP15870592.1

申请日：2015-11-19

申请人： INTEL Corporation

发明人： ANDERS, Mark A. ,  KAUL, Himanshu ,  CHEN, Gregory K.

IPC分类号： G06F12/08 ,  G06F12/0806 ,  G06F12/0817 ,  G06F12/0893

公开(公告)号：EP3238391A1

公开(公告)日：2017-11-01

申请号：EP15874020.9

申请日：2015-11-25

申请人： INTEL Corporation

发明人： CHEN, Gregory K. ,  ANDERS, Mark A. ,  KAUL, Himanshu ,  KRISHNAMURTHY, Ram K. ,  KIM, Yejoong

IPC分类号： H04L12/771 ,  H04L12/931 ,  G06F13/14

CPC分类号： H04L49/109 ,  H04L45/60 ,  H04L49/60

摘要： A packet-switched reservation request to be associated with a first data stream is received. A communication mode is selected. The communication mode is to be either a circuit-switched mode or a packet-switched mode. At least a portion of the first data stream is communicated in accordance with the communication mode.

摘要翻译： 接收与第一数据流相关联的分组交换预留请求。 选择通信模式。 通信模式是电路交换模式或分组交换模式。 根据通信模式传送第一数据流的至少一部分。

公开(公告)号：EP3235190A1

公开(公告)日：2017-10-25

申请号：EP15870583.0

申请日：2015-11-18

申请人： INTEL Corporation

发明人： KAUL, Himanshu ,  ANDERS, Mark A. ,  CHEN, Gregory K.

IPC分类号： H04L12/70 ,  H04L29/02

CPC分类号： G06F13/4022 ,  H04L12/54 ,  H04L49/10

摘要： An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

摘要翻译： 一种设备包括第一端口组，其包括输入端口和输出端口。 该装置还包括多个第二端口组。 每个第二端口组包括耦合到第一端口组的输出端口的输入端口和耦合到第一端口组的输入端口的输出端口。 多个第二端口组将以第一最大带宽进行通信，并且第一端口组以第二最大带宽进行通信，该第二最大带宽高于第一最大带宽。

公开(公告)号：EP3234783A1

公开(公告)日：2017-10-25

申请号：EP15870592.1

申请日：2015-11-19

申请人： INTEL Corporation

发明人： ANDERS, Mark A. ,  KAUL, Himanshu ,  CHEN, Gregory K.

IPC分类号： G06F12/08

CPC分类号： G06F12/0806 ,  G06F12/0824 ,  G06F12/0893 ,  G06F2212/1021 ,  G06F2212/284 ,  G06F2212/608 ,  Y02D10/13

摘要： A first pointer dereferencer receives a location of a portion of a first node of a data structure. The first node is to be stored in a first storage element. A first pointer is obtained from the first node of the data structure. A location of a portion of a second node of the data structure is determined based on the first pointer. The second node is to be stored in a second storage element. The location of the portion of the second node of the data structure is sent to a second pointer dereferencer that is to access the portion of the second node from the second storage element.

摘要翻译： 第一指针解引用程序接收数据结构的第一节点的一部分的位置。 第一个节点将存储在第一个存储元素中。 第一个指针是从数据结构的第一个节点获得的。 基于第一指针来确定数据结构的第二节点的一部分的位置。 第二节点将被存储在第二存储元件中。 数据结构的第二节点的该部分的位置被发送到将从第二存储元件访问第二节点的该部分的第二指针解除引用器。

公开(公告)号：EP4242838A2

公开(公告)日：2023-09-13

申请号：EP23182458.2

申请日：2018-03-26

申请人： INTEL Corporation

发明人： KAUL, Himanshu ,  ANDERS, Mark A. ,  MATHEW, Sanu K. ,  YAO, Anbang ,  RAY, Joydeep ,  TANG, Ping T. ,  STRICKLAND, Michael S. ,  CHEN, Xiaoming ,  SHPEISMAN, Tatiana ,  APPU, Abhishek R. ,  KOKER, Altug ,  SINHA, Kamal ,  VEMBU, Balaji ,  GALOPPO VON BORRIES, Nicolas C. ,  NURVITADHI, Eriko ,  BARIK, Rajkishore ,  LIN, Tsung-Han ,  RANGANATHAN, Vasanth ,  JAHAGIRDAR, Sanjeev

IPC分类号： G06F9/30

摘要： One embodiment provides for a processing unit comprising fetch and decode circuitry to fetch and decode a floating-point multiply-accumulate instruction; and execution circuitry to execute the floating-point multiply-accumulate instruction. The execution circuitry comprises mantissa multiplication circuitry, wherein the mantissa multiplication circuitry is shared with an integer datapath of the execution circuitry, wherein responsive to the floating-point multiply-accumulate instruction, the mantissa multiplication circuitry is to perform a multiplication operation with a mantissa value of each 16-bit floating-point data element of a first plurality of 16-bit floating-point data elements and a mantissa value of a corresponding 16-bit floating-point data element of a second plurality of 16-bit floating-point data elements to generate a corresponding plurality of mantissa results; exponent processing circuitry, responsive to the floating-point multiply-accumulate instruction, to perform an operation with an exponent value of each 16-bit floating-point data element of the first plurality of 16-bit floating-point data elements and an exponent value of each corresponding 16-bit floating-point data element of the second plurality of 16-bit floating-point data elements to generate a corresponding plurality of exponent results; circuitry to process the plurality of mantissa results and the plurality of exponent results to generate a corresponding floating-point product; and adder circuitry to generate a plurality of result floating-point values, each result floating-point value comprising a sum of one or more floating-point products of the plurality of floating-point products and a corresponding accumulated floating-point value of a plurality of accumulated floating-point values.

公开(公告)号：EP3238390A1

公开(公告)日：2017-11-01

申请号：EP15873990.4

申请日：2015-11-24

申请人： INTEL Corporation

发明人： CHEN, Gregory K. ,  ANDERS, Mark A. ,  KAUL, Himanshu ,  KRISHNAMURTHY, Ram K. ,  STILLMAKER, Aaron T.

IPC分类号： H04L12/771 ,  H04L12/931 ,  G06F13/14

CPC分类号： H04L47/625 ,  G06F15/7825 ,  H04L12/6402 ,  H04L47/72 ,  H04L49/30

摘要： A first packet-switched reservation request is received. Data associated with the first packet-switched reservation request is communicated through a first circuit-switched channel according to a best effort communication scheme. A second packet-switched reservation request is received. Data associated with the second packet-switched reservation request is communicated through a second circuit-switched channel according to a guaranteed throughput communication scheme.

摘要翻译： 接收到第一分组交换预约请求。 根据尽力而为通信方案通过第一电路交换信道传送与第一分组交换预留请求相关联的数据。 接收到第二分组交换预留请求。 根据保证的吞吐量通信方案通过第二电路交换信道传送与第二分组交换预留请求相关联的数据。

公开(公告)号：EP3230818A1

公开(公告)日：2017-10-18

申请号：EP15867374.9

申请日：2015-11-11

申请人： Intel Corporation

发明人： CHEN, Gregory K. ,  ANDERS, Mark A. ,  KAUL, Himanshu

IPC分类号： G06F1/12

CPC分类号： H03K5/135 ,  G06F5/10 ,  G11C8/18 ,  G11C19/287 ,  H03K2005/00013

摘要： A signal comprising a first edge and a second edge is received. The first edge of the signal is synchronized with a first clock and the synchronized first edge of the signal is passed to an output. The synchronization results in a delay of the first edge of the signal. The second edge of the signal is passed to the output. The passed second edge of the signal has a delay that is less than the delay of the first edge of the signal by at least one clock cycle of the first clock.

摘要翻译： 接收包括第一边缘和第二边缘的信号。 信号的第一个边沿与第一个时钟同步，信号的同步的第一个边沿传送到输出。 同步会导致信号的第一个边沿延迟。 信号的第二个边沿被传递到输出端。 信号的第二个边沿的延迟小于第一个时钟周期的至少一个信号的第一个边沿的延迟。