公开(公告)号：EP1198747A1

公开(公告)日：2002-04-24

申请号：EP99902317.9

申请日：1999-01-15

申请人： INTEL CORPORATION

发明人： KRICK, Robert, F. ,  HINTON, Glenn, J. ,  UPTON, Michael, D. ,  SAGER, David, J. ,  LEE, Chan, W.

IPC分类号： G06F9/38

CPC分类号： G06F9/3808 ,  G06F9/3802 ,  G06F9/3836 ,  G06F12/0875

摘要： A cache memory (10) is constituted with a data array (14) and control logic (26). The data array (14) includes a number of data lines, and the control logic (26) operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more basic blocks of instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.

公开(公告)号：EP0783735B1

公开(公告)日：2011-08-24

申请号：EP95931580.5

申请日：1995-08-24

申请人： Intel Corporation

发明人： GLEW, Andrew F., Apartment 24 ,  HINTON, Glenn, J.

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3857 ,  G06F12/0804 ,  G06F12/0888

摘要： A memory-type value identifying the type of memory contained with a range of memory locations is explicitly stored within a microprocessor (200-216). Prior to processing a memory micro-instruction such as a load or store, the memory-type is determined (214-216) for the memory location identified by the memory micro-instruction. Once the memory-type is known the memory micro-instruction is processed (218-230) in accordance with any one of a number or processing protocols including write-through processing (220), write-back processing (222), write-protect processing (224), restricted-cacheability processing (226), uncacheable speculatable write-combining processing (230), or uncacheable processing (228). By providing memory-type information explicitly within the microprocessor the protocol by which the micro-instruction is processed may be efficiently tailored to the memory-type. In an exemplary embodiment, the microprocessor is an out-of-order microprocessor (200) capable of generating speculative memory microinstructions (202-204).

公开(公告)号：EP2761464A1

公开(公告)日：2014-08-06

申请号：EP11873012.6

申请日：2011-09-30

申请人： Intel Corporation

发明人： RAMANUJAN, Raj, K. ,  AGARWAL, Rajat ,  HINTON, Glenn, J.

IPC分类号： G06F12/00 ,  G06F13/14 ,  G11C7/10

CPC分类号： G06F12/0811 ,  G06F12/0246 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2212/205 ,  G06F2212/283 ,  G06F2212/6046 ,  G06F2212/621 ,  G06F2212/7201 ,  G11C7/1045 ,  G11C7/1072 ,  G11C13/0004 ,  G11C14/0045

摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as "far memory." Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as "near memory." In one embodiment, the "near memory" is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

公开(公告)号：EP2761466B1

公开(公告)日：2020-08-05

申请号：EP11873218.9

申请日：2011-09-30

申请人： Intel Corporation

发明人： RAMANUJAN, Raj, K. ,  AGARWAL, Rajat ,  CHENG, Kai ,  POLEPEDDI, Taarinya ,  RAAD, Camille, C. ,  ZIMMERMAN, David, J. ,  SWAMINATHAN, Muthukumar, P. ,  ZIAKAS, Dimitrios ,  KUMAR, Mohan, J. ,  COURY, Bassam N ,  HINTON, Glenn, J.

IPC分类号： G06F12/00 ,  G11C7/10 ,  G06F12/08

公开(公告)号：EP0783735A1

公开(公告)日：1997-07-16

申请号：EP95931580.0

申请日：1995-08-24

申请人： INTEL CORPORATION

发明人： GLEW, Andrew F., Apartment 24 ,  HINTON, Glenn, J.

IPC分类号： G06F9 ,  G06F12

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3857 ,  G06F12/0804 ,  G06F12/0888

摘要： A memory-type value identifying the type of memory contained with a range of memory locations is explicitly stored within a microprocessor (200-216). Prior to processing a memory micro-instruction such as a load or store, the memory-type is determined (214-216) for the memory location identified by the memory micro-instruction. Once the memory-type is known the memory micro-instruction is processed (218-230) in accordance with any one of a number or processing protocols including write-through processing (220), write-back processing (222), write-protect processing (224), restricted-cacheability processing (226), uncacheable speculatable write-combining processing (230), or uncacheable processing (228). By providing memory-type information explicitly within the microprocessor the protocol by which the micro-instruction is processed may be efficiently tailored to the memory-type. In an exemplary embodiment, the microprocessor is an out-of-order microprocessor (200) capable of generating speculative memory microinstructions (202-204).

公开(公告)号：EP2761464B1

公开(公告)日：2018-10-24

申请号：EP11873012.6

申请日：2011-09-30

申请人： Intel Corporation

发明人： RAMANUJAN, Raj, K. ,  AGARWAL, Rajat ,  HINTON, Glenn, J.

IPC分类号： G11C13/00 ,  G06F12/0893

CPC分类号： G06F12/0811 ,  G06F12/0246 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2212/205 ,  G06F2212/283 ,  G06F2212/6046 ,  G06F2212/621 ,  G06F2212/7201 ,  G11C7/1045 ,  G11C7/1072 ,  G11C13/0004 ,  G11C14/0045

摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

公开(公告)号：EP2761466A1

公开(公告)日：2014-08-06

申请号：EP11873218.9

申请日：2011-09-30

申请人： Intel Corporation

发明人： RAMANUJAN, Raj, K. ,  AGARWAL, Rajat ,  CHENG, Kai ,  POLEPEDDI, Taarinya ,  RAAD, Camille, C. ,  ZIMMERMAN, David, J. ,  SWAMINATHAN, Muthukumar, P. ,  ZIAKAS, Dimitrios ,  KUMAR, Mohan, J. ,  COURY, Bassam N ,  HINTON, Glenn, J.

IPC分类号： G06F12/00 ,  G11C7/10

摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”