公开(公告)号：EP3311401A1

公开(公告)日：2018-04-25

申请号：EP15896494.0

申请日：2015-06-22

Applicant: Intel Corporation

Inventor： CHEN, Yi Wei ,  PHOA, Kinyip ,  NIDHI, Nidhi ,  LIN, Jui-Yen ,  SHIH, Kun-Huan ,  YANG, Xiaodong ,  HAFEZ, Walid M. ,  TSAI, Curtis

IPC: H01L21/60

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76898 ,  H01L27/0629 ,  H01L27/1203 ,  H01L28/90 ,  H01L29/945

Abstract: Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.